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Computer Organization VonNeuman VHDL Arrays

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The position within the array is given by a scalar value called its index. ... variable index : mem_add := (x'ff', x'ff', x'ff', x'ff', x'ff', x'ff', x'ff', x'ff' ... – PowerPoint PPT presentation

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Title: Computer Organization VonNeuman VHDL Arrays


1
Computer Organization (Von-Neuman)VHDL (Arrays)
Arrays are a collection of values of the same
type. The position within the array is given by a
scalar value called its index. type WORD is
array (0 to 31) of bit -- index from 0 to
31 type WORD is array (31 downto 0) of bit --
index values start at 31 type CONTROLLER_STATE
is (initial, idle,active, error) -- index not a
value
2
Computer Organization (Von-Neuman)VHDL (Memory
Example)
entity memory is port (ADDRESS in bit_vector(0
to 3) DATA out bit_vector(0 to 7) end
memory library vector use vector.functions.all
architecture beh of mem is begin memprocess
process (ADDRESS) is subtype byteword is
bit_vector (0 to 7) type mem_add is array (0 to
8) of byteword variable index mem_add
(xff, xff, xff, xff, xff, xff, xff,
xff) begin DATA lt index (to_natural
(ADDRESS)) end process end beh

Entity Memory
4
Address
Arch Memory
8
0000 0001 0010 0011 0100 0101 0110 0111 1000
Data
3
Computer Organization (Von-Neuman)VHDL (Block
Statement)
  • Block Statement (p188 Bhasker)
  • Statements between are optional
  • Disables signal drivers by using guards.
  • To limit the scope of declarations, including
    signal.
  • To represent a portion design.
  • Declarations within block end block are visible
    only within block.
  • If a guard-expression appears in the block
    statement, it means that any statement that is
    guarded (B), will be assigned to the target
    signal(A) when the guard-expression is true (Alt
    guarded B)
  • SYNTAX
  • block-label block(guard-expression) is
  • block-header
  • block-declarations
  • begin
  • concurrent-statements
  • end block block-label
  • GATED INVERTER EXAMPLE
  • B1 block (STROBE 1)
  • begin
  • Z lt guarded not A
  • end block B1


4
VHDL Assert
  • Syntax.. assert boolean-expression
  • report string-expression
  • severity expression
  • If the value of the Boolean expression is false,
    the report message is printed along with the
    severity level.
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