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Impact of VLSI Technology

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Substrate doping. Current per device. Gate capacitance. Transistor on-resistance ... 1 RISC core (floating point), 4 DSP PEs with integer units, 4 memory modules. ... – PowerPoint PPT presentation

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Title: Impact of VLSI Technology


1
Impact of VLSI Technology
  • Yu Hen Hu

2
Outline
  • Scaling of VLSI Technology
  • Scaling Effect on Circuit Parameters
  • Scaling Effect on Programmable VSP Architecture

3
MOS Scaling Effect
  • Devise dimensions
  • Supply voltage
  • Substrate doping
  • Current per device
  • Gate capacitance
  • Transistor on-resistance
  • Intrinsic gate delay
  • Power dissipation per gate
  • Area per device
  • 1/s (sgt1)
  • 1/s
  • s
  • 1/s
  • 1/s
  • 1
  • 1/s
  • 1/s2
  • 1/s2

4
Video Signal Processing Architecture
  • ASC (TI), IDSP (NTT)
  • Multiple, pipelined arithmetic units,
  • Interleaved dual-port memory.
  • VSP1 (Philips)
  • Crossbar connection of memory and Pes
  • MVP (TI 32080)
  • 1 RISC core (floating point), 4 DSP PEs with
    integer units, 4 memory modules.
  • Crossbar interconnection switches.

5
Scaling Effects on Circuit/Architecture
  • Interconnect cross section
  • Long wire chip size
  • Long wire delay
  • short wire delay
  • Processor delay
  • Memory delay/Proc. delay
  • 1/s2
  • sm
  • AsmB/s
  • 1
  • 1/s
  • Cs D

6
Interconnection Delay
  • Elmore delay
  • t1 R1(C1C2C3C4)R2(C2C3C4)R3C3

OUT1
R1
R2
R3
C3
C2
C1
R4
C4
7
Interconnection Delay (2)
  • R ? L/(WH) ? s
  • C ? L (W/toxf H/Dh) ? 1/s
  • Hence RC time constant is independent of scaling!
  • However, as scaling factor s increases, often
    chip area does not descrease, and rather
    increases. Hence the global wires (e.g. clock)
    will have added delay (a factor sm) as a result
    of scaling!

8
Impacts on Architecture
  • Processor delay reduces (1/s) since transistor
    gate delay smaller, clock higher, voltage lower
  • Memory delay is determined by the BIT line. It
    should reduce if memory size unchanged. But will
    increase if memory size increases.
  • Interconnection network delay will stay the same
    or larger (when larger network used)

9
Conclusion
  • Scaling of device parameter will impact on
    circuit parameters (delay) which in turn impact
    on architectural decisions.
  • As devices feature sizes continue to shrink, new
    architectural style must be developed to exploit
    most benefit from scaling.
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