A 64bit PCI DDR SDRAM Controller

1
A 64-bit PCI DDR SDRAM Controller

• Max Baker Christopher Case
• EE4340 Prof. Ken Sheppard
• May 12th , 2004

2
Specifications

• Create a working PCI DDR SDRAM controller using
  pre-existing hardware
• 64-Bit, 66 MHz PCI Bus
• 133 MHz DDR SDRAM
• Read and Writes from the PCI bus to the card
• Optional Burst Mode implementation

3
Technical Details

• Dell 2GHz Xeon running Fedora Core
• 64 Bit, 66MHz PCI Bus
• PCI DDR board designed last semester
• Micron MT46V16M16 (4 Meg x 16 x 16 banks)
• 16 bit, 133 MHz, 64 MB DDR SDRAM
• Xilinx XC2V1000-5FG456 Virtex-ii FPGA
• 1M Gates, 8 DCMS, 432 I/O Pads
• Jungo Windriver development Toolkit (32 bit)

4
Top Level Design
5
PCI DDR Bridge State Machine
6
Dataflow Steps

• Analyze
• Elaborate
• Simulate
• Synthesis
• Place and Route
• Download to board
• Ready to run and test design

7
Conclusion

• 32 bit reads and writes work
• Runs at required clock speeds
• Improvements
• Enable PCI Bursting
• Fix driver for 64 bit transfers
• Write a RAM disk interface driver