Class Information

1
Lecture 6

• 9/23/02

2
Class Information

• Homework
• Due October 3 (Thursday).
• Simulation Exercise 4.1 and 4.3.
• Synthesis Exercise 5.1 and 5.2.
• Quiz 2
• September 1 (Tuesday).

3
Review HDL Alphabet Soup

• Synthesis
• Inference
• Target technology
• Logic netlist

4
What is Synthesis?

• Synthesis transforms VHDL code into a hardware
  netlist.
• A netlist is a list of hardware components and
  their interconnections.
• Hardware components available to synthesis tool
  are determined by the target technology.
• For Xilinx 4K FPGA family, hardware component is
  a CLB (or its sub-parts).
• Multiple synthesis solutions are possible and
  thousands of solutions are tried by the tool.

5
Imagine yourself being a synthesis tool...
entity control is generic ( N integer 32
-- crossbar size logN integer 5) --
self-explanatory! port ( clk, reset in
std_logic -- clock signal (edge-trigd.) eop,
rdy in std_logic_vector (N-1 downto 0) adr
in std_logic_vector (NlogN-1 downto 0)
eni, eno out std_logic_vector (N-1 downto 0)
pti, pto out std_logic_vector(NlogN-1 downto
0) end control architecture behavior of
control is signal eni_reg std_logic_vector(N-
1 downto 0) signal eno_reg
std_logic_vector(N-1 downto 0) type
port_vector is array (INTEGER range ltgt) of
std_logic_vector (logN-1 downto 0) signal
pti_reg port_vector (N-1 downto 0) signal
pto_reg port_vector (N-1 downto 0) signal
adr_reg port_vector (N-1 downto 0) begin
eni lt eni_reg eno lt eno_reg gen0 for i
in 0 to N-1 generate gen1 for j in 0 to
logN-1 generate adr_reg(i)(j) lt
adr(logNij) pti(logNij) lt
pti_reg(i)(j) pto(logNij) lt
pto_reg(i)(j) end generate gen1 end
generate gen0 main process variable i
integer range N-1 downto 0 -- main index
begin if (iN-1 or reset'0') then i0
else ii1 end if wait until (clk'event
and clk'1') for j in N-1 downto 0 loop
if (reset'0') then eni_reg(j)
lt '0' eno_reg(j) lt '0'
elsif (eni_reg(j)'1' and eop(j)'1') then
eni_reg(j) lt '0'
eno_reg(CONV_INTEGER(UNSIGNED(pti_reg(j)))) lt
'0' end if end loop if
(eni_reg(i)'0' and rdy(i)'1') then if
(eno_reg(CONV_INTEGER(UNSIGNED(adr_reg(i))))'0')
then pti_reg(i) lt adr_reg(i)
pto_reg(CONV_INTEGER(UNSIGNED(adr_reg(i))))
lt CONV_STD_LOGIC_VECTOR(i, logN)
eni_reg(i) lt '1' eno_reg(CONV_INTEGE
R(UNSIGNED(adr_reg(i)))) lt '1' end
if end if end process end behavior
I cant
6
Is synthesis easy for computers?

• 55 lines of VHDL code (above) synthesized for 3
  days and crashed my computer !
• Complete rewrite broke this code into 65
  independent coding blocks.
• Each block was synthesized separately.
• Final solution was 30,000 transistors (layout on
  the right).
• This is a true story!

7
A simpler example
Questions Where do I start? How many bits to
allocate for signals? Can we share the adder
circuit? What type of adder should be used?
8
Inference from Signal Declaration

• The implementation of a signal as wire, latch of
  flip-flop depends on how the signal is used (e.g.
  not on signal declaration).
• Signals declaration tells us the number of bits
  required to represent the signal.
• Unbound integer requires 32 bits.
• Synthesis tools have special commands to encode
  user-defined types (for faster state-machines).

9
Whats not supported?

• Some data types are not supported.
• Explicit signal initialization is not supported.
• Implicit signal initialization is not supported.
• Everything becomes IEEE1164 bits and is
  initialized to U at start of simulation.

10
Initialization before and after synthesis

• Result starts as UUUUUUUUUUUU (12 Us) both
  before after.
• Count starts as 2321 before UU (32 Us)
  after.
• Index starts as 0 before UUUUUU (6 Us)
  after.
• Next_state starts as STATE0 before and UU
  after. But if we ask synthesis tool to one hot
  encode we get UUUU after!)

11
Inference from concurrent signal assignment
Synthesized logic schematic
FPGA Implementation
12
Putting it all together

• A CLB can implement any boolean function of five
  variables and some boolean functions of up to 9
  variables.
• The outputs of the CLB can be asynchronous or
  registered (using flip-flops).
• Each CLB needs 40 bits for LUT and 10-20 bits for
  multiplexor configuration. These are set at
  power-on.
• Rule of thumb 20 configuration bits required per
  logic gate.

13
Configuring Function Generator

• Any logic function with up to 4 inputs can be
  implemented by lookup.
• Requires 16 configuration memory bits.

14
Full Adder Example
Synthesized logic schematic
FPGA Implementation
15
Inference from conditional signal assignment

• Hardware implementation is a priority encoder
  that preserves the order of conditional
  expressions in your VHDL code.

16
Example
Synthesized logic schematic
FPGA Implementation
17
Inference from selected signal assignment

• Hardware implementation is a multiplexer that
  preserves the order is not important principle
  of selected signal assignment.

18
Example of selected signal assignment
entity mux is port ( sel in std_logic_vector(
1 downto 0 ) Din in std_logic_vector ( 3
downto 0 ) Dout out std_logic) end entity
architecture my_mux_behavior of mux is begin
with sel select Dout lt Din(3) when "11",
Din(2) when "10", Din(1) when "01", Din(0)
when "00", X when others end
my_mux_behavior
19
Are these equivalent?
entity mux is port ( sel in std_logic_vector(
1 downto 0 ) Din in std_logic_vector ( 3
downto 0 ) Dout out std_logic) end entity
architecture my_mux_behavior of mux is begin
Doutlt Din(3)when sel"11 else Din(2)when
sel"10"else Din(1)when sel"01"else
Din(0)when sel"00"else X' --if all fails
then X end my_mux_behavior end my_mux_behavior
entity mux is port ( sel in std_logic_vector(
1 downto 0 ) Din in std_logic_vector ( 3
downto 0 ) Dout out std_logic) end entity
architecture my_mux_behavior of mux is begin
with sel select Dout lt Din(3) when "11",
Din(2) when "10", Din(1) when "01", Din(0)
when "00", X when others end
my_mux_behavior
Yes, but the selected CSA is better method!