Random Number Generator

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Random Number Generator
March 1, 2006 Component Layout and Floorplan

• Dmitriy Solmonov W1-1
• David Levitt W1-2
• Jesse Guss W1-3
• Sirisha Pillalamarri W1-4
• Matt Russo W1-5
• Design Manager Thiago Hersan

Project Objective Create a Cryptologically
Secure Pseudo-Random Number Generator
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Agenda

• Status
• Design Decisions
• Critical Layouts
• Power and Timing Analysis

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Status

• Former
• C implementation
• Architecture
• Behavioral Design and Simulation
• Gate-Level Design and Simulation
• Preliminary Floorplan
• Schematic Design and Simulation
• Currently
• Layout (15,800 of 33,225)
• SRAM
• Low 10 bits of the adder
• D-Flip Flop
• Some basic gates (as we need them)
• Awaiting
• Extraction, LVS, post-layout simulation

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Design Decisions

• JKFF
• Need to be redesigned

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JKFF

• Now using master-slave n-pass latches.
• 3 simple gates at input perform JK logic.
• Pros, cons

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CS4_1, CS6
New Completed Layouts
32-bit adder
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CS4_1 Block
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3 Bit Add Block
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SRAM New Layouts
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Floorplan Schematic
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Datapath
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Putting it All Together (updated)
3 bit low 4 bits
71uW 100uW
138 132
594 594
298ns 397ns
200ps
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Thanks! Any Questions?