The CMS SiliconTracker Data Acquisition System

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The CMS SiliconTrackerData Acquisition System
Electronic Systems Design Group Electronic
Systems Support Group Microelectronics Design
Group (CERN, PPD, Imperial College London)
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CMS Front End Driver
9U VME board
Off Detector Data Acquistion
Extract Interesting Silicon Detector Data
System needs 500 boards
by end 2006
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What? LHC Facility
Large Hadron Collider Facility
Particle Accelerator
Tunnel 27 km
100 m underground
CERN Geneva
Long term project
Starts Operation 2007
CMS
Superconducting Magnets
Counter rotating Proton beams bunch collision
rate 40 MHz
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LHC Collision
E mc2
7 TeV
7 TeV
Fundamental Question for Large Hadron
Collider What is the origin of mass?
Search for Higgs Particle
Collision Event
Study products of collisions - Look for Rare New
particles
40 Million such collisions per second But perhaps
only a few dozen Higgs per year!
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What? CMS Experiment
Several major Particle Detectors
Beams collide
Compact Muon Solenoid
12,000 tons Superconducting Solenoid Magnet 4
Tesla 20,000 Amps
500 M
Will operate for gt 15 Years
The total mass of CMS is approximately 12500
tonnes - double that of ATLAS (even though
ATLAS is 8x the volume of CMS)
The amount of iron used as the magnet return yoke
is roughly equivalent to that used to build the
Eiffel Tower in Paris
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What? CMS Experiment
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What? CMS Experiment
Silicon Tracker
Compact Muon Solenoid
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What? Silicon Tracker
220 m2 of silicon sensorsgt 9 million silicon
strips
Charged Track reconstruction. Very high
Granularity.
Front End Electronics
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APV Analogue Pipeline Chip
APV25 ASIC MEDG Design Analogue PIPELINE
clocked _at_ 40 MHz On Detector v High
Radiation Low Power Low Noise 0.25 IBM deep
sub-micron process Each chip handles 128
strips Holds each 25 nsec sample till Trigger
slice Serial output of all 128 strips at 100 kHz
Pipeline
Pre-Amp
Total gt 70,000 chips gt gt 9 million strips _at_
100 kHz
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Tracker Readout Electronics

• Off Detector No Radiation (counting room)
• Optical links transmit equivalent to
• 1.5 TeraBytes/sec
• 450 Front End Drivers (FEDs)

DCU
Lasers
APV MUX 21
70 metres
40,000 fibres
PLL
FED
Detector
Front End Module

• On Detector High Radiation
• 9M silicon strips
• 73k APV25 readout chips
• Analogue readout via 43k optical readout links

x8
x96
FPGA
100 kHz events / sec Digitisation Digital Process
RAM
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Front End Driver
96 optical fibres inputs, each a Multiplexed pair
of APVs 25,000 strips 8 front end blocks each
driven by a 12 way optical ribbon cable Raw input
data rate 3.4 GB/s. Extract hit
strips Processed Output rate lt 200 MB/s
VME FPGA
Front-End data processing FPGA
Output to DAQ
Opto Receivers
Event Builder FPGA
96 ADC channels
Modular FE Unit
Power
Double Sided Board
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Front End (FE) Unit on FED

• To extract hit need to perform
• Common mode subtraction
• - Pedestal subtraction
• - Cluster finding
• - Sync checking

Digital header
128 analogue values (one for each microstrip)
Signal magnitude
MIP
Time
Opto-to-electrical conversion
Digitise sync data
Find hit clusters
Opto-RX, 12 way
3 x Delay FPGA (ADC clk timing)
Virtex II, 2M gate FPGA performs signal processing
Optical ribbon cable input
6 x Dual 40MHz, 10bit ADCs
Analogue circuitry duplicated on secondary side
12 x Buffers
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Digital Logic FPGAs
Delay x 24
FE x 8
CDAQ
lt 200 MB/s
VME
34 Field Programmable Gate Arrays on board
FPGA gt Flexibility Algorithms Design
Versioning Q. Maintenance over 15 Years ?
Event Builder
Xilinx Virtex-II
40k -gt 2M gates
NB Most Firmware was only implemented after
prototype board manufacture.
Delay FPGA ADC Coarse and Fine Clock Skewing.
FE FPGA Scope and Frame Finding modes. BE
FPGA Event building, buffering and formatting.
VME FPGA Controls and Slow Readout path.
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Front End Driver
For 450 FEDs 30 VME crates 12 Racks
electronics Installation in Q2-gtQ3 / 2006
100 GB/s output
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Board Manufacture
High density components. Close up of analogue
section on primary side Almost all components on
board are Surface Mount.
Value is in the COMPONENTS
Design for TEST

• Board parameters
• - 9U x 440 mm VME64x form factor
• - Optical/Analogue/Digital logic 96 ADC
  channels
• Double-sided (secondary side with half of
  analogue channels)
• 6,000 components (majority of passives 0402)
  (finest pitch lt 20 thou)
• 25,000 tracks
• 37 BGAs (typical FPGA 676 pins on 1mm pitch).
  All BGAs located on primary side.
• 14 layers (incl. 6 power gnd)
• controlled impedance

440 FED boards required for full CMS Tracker
readout
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FED Contract

• 2002-2003 Mixed experiences with Prototype
  Production.
• CMS FED Production Contract process. (with EID
  Procurement Officer)
• PCB Framework contract for EID. Using CMS FED as
  Reference Design for Quotes.
• One Stop Shop PCB Component Procurement
  Assembly (Test)
• Process took 18 months
• Followed European Union Tender Procedures
• Q4/2003 Inspecting facilities at candidate
  companies
• Q1/2004 Place OJEC advert, invite Expressions
  of Interest.
• Q3/2004 Dispatch calls for Quotes.
• Q4/2004 Select 3 Framework companies.
• Q1/2005 Detailed negotiations with one company
  re Testing, schedulesetc
• Q2/2005 Signed contract. Within our predicted
  budget.

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Assembly Quality Controls
Surface mount assembly checking with Fully
Automatic Optical Inspection (AOI) (Diagnosis
VisionPoint, 100 components per minute) Detects
component misplacements, incorrect part nrs, poor
solder joints, solder bridges.
SMT Reflow Temp Profiling
BGA assembly verified with 3D X-Ray..
Ersascope
Final (optional) test of fully assembled boards
using a Fixtureless Test Station.
(example is not from a FED)
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Acceptance Testing
0. Quality Controls
during Assembly
process
AOI, X-ray
1. Custom CMS Tests
At Assembly Plant
Boundary Scan Analogue
FED
Assembly Company
2. Tests at RAL
Optical, SLINK, Full crate
3. Tests at CERN
Prevessin 904
B186 Tracker Integration
RAL Test Rig
4. Installation at CMS
USC55
Pipeline with each stage taking 1 month and
containing 50 FEDs
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Testing at Assembly Plant
Custom LabView Application on Linux PC
Test Results stored as XML files
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FED Project Status
Total of 500 (incl. 50 spares) x 9U FEDs.

• 1st batch of 50 FED boards are all at RAL and
  almost all pass tests.
• 2nd batch of 50 most at RAL and pass tests.
• 3rd batch of 50 many at RAL remaining in test at
  Assembly.
• 4th batch of 50 assembly is in progress.
• Board yield is good so far. 5 still requiring
  further attention at RAL.
• Test systems installed at Assembly plant are
  working well.

Silicon Tracker Ready
mid 2007 LHC running
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Further Information
Information on the FED board
www.te.rl.ac.uk/esdg/cms-fed/qa_web
Information on CMS and CERN
http//cmsinfo.cern.ch/outreach/
Or contact
j.coughlan_at_rl.ac.uk
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CMS Collaboration
CCLRC Rutherford Appleton Laboratory Imperial
College Brunel University