Acyclic Modeling of Combinational Loops

1
Acyclic Modeling of Combinational Loops

• Amit Gupta (Tabula Inc.)
• Charley Selvidge (Mentor Graphics Inc.)
• ICCAD 2005, San Jose CA USA

2
Feedback Loops are Annoying!

• Scheduled cycle accurate simulators
• Statically scheduled emulation
• Event driven simulation
• Analog behavior of non oscillating feedback loops
  when they are pipelined.

3
Possible Solution

• Encapsulating loops within a chip for statically
  scheduled emulation
• State machine to wait for the loops to stabilize
  (non real time)
• Convert those loops which are not really loops
  (topological loops)

FOR MORE INFO...
Reference 2,4,5,6 from the paper
4
Our Contribution

• An Algorithm to convert arbitrary feedback loops
  statically, to Acyclic components.
• Strengths
• An efficient algorithm for industrial scale
  designs.
• Handle any types of loops (with or without
  states)
• Weakness
• Each feedback path treated separately.

5
Our Contribution

• Any output of a combinational loop can be
• modeled as a state holding elements with the
• following properties
• The output can be computed independent of the
• feedback path for some assignment to non cyclic
• inputs to the loop
• For all other assignments to the non cyclic
• inputs, the output hold its previous value.

6
Monotonic Feedback Loops

• Representation of Feedback Loops
• X F(I). X G(I).(X) C(I)
• I is locally independent input set
• Really two feedback paths
• Y1 G(I).(X), Y2 F(I).X
• X F(I).X Y1 C(I)
• X G(I).(X) Y2 C(I)
• Non Oscillating Loops
• X F(I).X C(I)

7
Modeling Feedback Paths

• X F(I). X C(I)
• X F(I).X.(C(I) C(I)) C(I)
• X F(I).C(I).X C(I)

C(I)
X
F(I)
X
C(I)
F(I).C(I)
8
Gating Condition of Latch

• Function of input set (I), for which the the
  feedback path is the controlling input.
• For an And/Inv based netlist, the non feedback
  input 1, results in feedback path being
  controlling input.
• For arbitrary logic gate (K-input Lookup table),
  Fig-5 shows an algorithm to compute the
  controlling condition.
• Essentially, a decomposition of logic elements in
  the feedback loop to a multiplexer.
• All the selects of multiplexer selects feedback
  path to mutually create gating condition of the
  latch.

9
Data Condition For Latch

• X (F(I).C(I)).X C(I)
• Data X X 0
• Data X X dont care (F(I) 0).
• The Data condition of the latch is used, only
  when latch is open

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Feedback Loop Transformation..
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Feedback Loop Transformation..
S1
S2
S3
12
Feedback Loop Transformation..
Y
Z
S1
S2
S3
1bx
X
Y
Z
S1
S2
S3
S1S2S3
S1
S2
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Oscillating Loops

• If the feedback loop is statically determined to
  be oscillatory
• User directive that all possibly oscillatory
  loops will never close
• Generate the Acyclic circuit using latch and keep
  the latch always open
• Never Hold the oscillatory state!!

14
Experimental Results

• Implemented for VStation time multiplexed Fpga
  System.
• Results for some industrial scale designs

15
Summary

• Combinational Loops hold state when they are
  closed.
• Latch is the ideal primitive to model the state
  of the loops.
• Efficient algorithm to handle commercial design.
• The circuit for latch gate condition can possibly
  be optimized further.