ASIC design first trial

1
ASIC design (first trial)
Chip area 8 mm x 2.5 mm 2-channel iCDS 1.5 mm x
0.5 mm
Collaboration with Ikeda-sensei (JAXA) who
developed Open-IP
2
Packaging (Steady Design corp.)
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Result of M01 using the NeXT1 chip
CCD-NeXT1 Pixel size 12 mm x 12 mm of
pixels 2000 x 2004 of read-out 2
M01 functioned properly in photon count mode.
However, the noise level is large (55 electrons).
This is due to the chip design. We are now
developing new ASIC chip as the second trial.