CMPUT329 Fall 2003

1
CMPUT329 - Fall 2003

• TopicF Static and Dynamic Memories
• José Nelson Amaral

2
Reading Assignment
Chapter 10 of Wakerly
Sections 10.1, 10.2, 10.3, 10.4
3
ALUOp
PcWrite
Control Unit
PcWriteCond
PCSource
IorD
ALUSelA
MemRead
TargetWrite
RegWrite
MemWrite
Target
IRWrite
MemtoReg
ALUSelB
RegDst
Conc/ Shift left 2
PC
I25-21
Read register 1
Read address
Instruction 31-26
Read data 1
I20-16
Zero
Read register 2
Memory
Write address
ALU result
Instruction 25-0
Write register
Read data 2
ALU
MemData
Instruction register
Write data
4
Write data
15-11
Registers
0
M u x
1
32
Sign ext.
ALU control
I15-0
Shift left 2
4
ALUOp
PcWrite
Control Unit
PcWriteCond
PCSource
IorD
ALUSelA
MemRead
TargetWrite
RegWrite
MemWrite
Target
IRWrite
MemtoReg
ALUSelB
RegDst
Conc/ Shift left 2
PC
I25-21
Read register 1
Read address
Instruction 31-26
Read data 1
I20-16
Zero
Read register 2
Memory
Write address
ALU result
Instruction 25-0
Write register
Read data 2
ALU
MemData
Instruction register
Write data
4
Write data
15-11
Registers
0
M u x
1
32
Sign ext.
ALU control
I15-0
Shift left 2
5
EPROMs (Erasable Programmable Read Only Memories)
A0-A15 Address Bus D0-D7 Data Bus CS Chip
Select OE Output Enable
6
Address Decoding on a Microprocessor System
microprocessor
A0
A1

A19
74x139
1Y0 1Y1 1Y2 1Y3
1G
1A 1B
D0
D1

D7
READ
WRITE
7
The 74x139 Decoder
8
The 74x139 Decoder
9
The 74x139 Decoder
10
The 74x139 Decoder
11
The 74x139 Decoder
1Y0_L
1G_L
1Y1_L
1Y2_L
1A
1Y3_L
1B
12
The 74x139 Decoder
1Y0_L
1G_L
1Y1_L
1Y2_L
1A
1Y3_L
1B
13
The 74x139 Decoder
1Y0_L
1G_L
1Y1_L
1Y2_L
1A
1Y3_L
1B
14
The 74x139 Decoder
15
The 74x139 Decoder
16
Address Decoding
We want to design a microprocessor-based system
with 128 Kbytes of EPROM using the 27256
EPROM chips that have an organization of 32K ? 8
bits. This particular microprocessor has a data
bus that is 8-bit wide and an address bus that is
20-bits wide. The EPROM is to be mapped to the
highest addresses of the memory address space.
17
Address Decoding
A memory address in this system has the following
format
32 Kbytes 32 ? 1024 25 ? 210 215 bytes Thus
we need 15 address lines to address 32 Kbytes.
18
Address Decoding
The 64K highest addresses are the following
addresses.
And the 128K highest addresses are
19
Address Decoding
Thus to verify if a memory access is to the
EPROM region, we can just verify if the address
lines A19, A18, and A17 are simultaneously 1
20
Address Decoding
To create a space of 128 Kbytes of EPROM with
chips that have 32 Kbytes capacity, we will need
four memory chips.
How can we use the address lines to identify
which memory chip is been accessed each time?
21
Address Decoding
The memory chip placed at the higher portion of
the address space contains the memory addresses
starting at
F8000
22
Address Decoding
Bank 3
F8000
FFFFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 0
E0000
E7FFF
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
23
Address Decoding
19
18
16
17
15
14
12
13
11
10
8
9
7
6
4
5
3
2
0
1
Bank 3
F8000
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FFFFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
19
18
16
17
15
14
12
13
11
10
8
9
7
6
4
5
3
2
0
1
Bank 2
F0000
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F7FFF
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
19
18
16
17
15
14
12
13
11
10
8
9
7
6
4
5
3
2
0
1
Bank 1
E8000
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EFFFF
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
19
18
16
17
15
14
12
13
11
10
8
9
7
6
4
5
3
2
0
1
Bank 0
E0000
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E7FFF
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
24
Address Decoding on a Microprocessor System
microprocessor
27256
27256
27256
27256
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1




D0
D0
D0
D0
A14
A14
A14
A14
O0

O0
O0
O0
A14
A14
A14
A14
D1
D1
D1
D1
O1
O1
O1
O1




A19
A19
O7
O7
O7
O7
CS
CS
CS
CS
D7
D7
D7
D7
OE
OE
OE
OE
D0
D0
D1
D1

D7
D7
READ
74x139
1Y0 1Y1 1Y2 1Y3
1G
WRITE
1A 1B
25
Types of Memories
Read/Write Memory (RWM)
we can store and retrieve data.
the
time required to read or write a bit of memory is
independent of the bits location.
Random Access Memory (RAM)

once a word is written to a location, it
remains stored as long as power is applied to the
chip, unless the location is written again.
Static Random Access Memory (SRAM)

the data stored at each location must
be refreshed periodically by reading it and then
writing it back again, or else it disappears.
Dynamic Random Access Memory (DRAM)
26
Random Access Memories (RAMs)
A Random-Access Memory (RAM) is so called to
contrast with its predecessor, the Serial-Access
Memory. In a serial access memory, memory
positions become available for reading on a
sequential fashion. Therefore to read an specific
memory position, the reader must wait a variable
time delay for the memory position to became
available.
27
Static-RAM Control Inputs
The outputs of memory chips are often connected
to a three-state bus, a bus that can be driven
by many devices. Therefore each memory chip
should drive the bus only when commanded to do so
by the control logic.
28
A 2n?b SRAM
2n ? b SRAM
Data outputs
CS
control inputs
OE
WE
29
SRAMs(Static Random Access Memories)
HM62256
HM628128
HM628512
2764
2764
2764
A0
A0
A0
A0
A0
A0
A1
A1
A1
A1
A1
A1



D0
D0
D0
IO0
IO0
IO0
A14
A16
A18
A14
A16
A18
D1
D1
D1
IO1
IO1
IO1



D7
D7
D7
IO7
IO7
IO7
30
Accesses to SRAM
Read An address is placed on the address inputs
while CS and OE are asserted. The latch
outputs for the selected memory
locations are delivered to DOUT.
Write An address is placed on the address inputs
and a data word is placed on DIN then
CS and WE are asserted. The latches in
the selected memory location open, and
the input word is stored.
31
0 1 2 3 4 5 6 7
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
3-to-8 decoder
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
0 1 1
2 1 0
A2 A1 A0
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
WR_L
WE_L
CS_L
IOE_L
OE_L
DOUT3
DOUT2
DOUT1
DOUT0
32
0 1 2 3 4 5 6 7
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
3-to-8 decoder
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
0 1 1
2 1 0
A2 A1 A0
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
WR_L
WE_L
CS_L
IOE_L
OE_L
DOUT3
DOUT3
DOUT3
DOUT3
33
0 1 2 3 4 5 6 7
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
3-to-8 decoder
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
0 1 1
2 1 0
A2 A1 A0
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
WR_L
WE_L
CS_L
IOE_L
OE_L
DOUT3
DOUT3
DOUT3
DOUT3
34
0 1 2 3 4 5 6 7
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
3-to-8 decoder
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
0 1 1
2 1 0
A2 A1 A0
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
WR_L
WE_L
CS_L
IOE_L
OE_L
DOUT3
DOUT3
DOUT3
DOUT3
35
SRAM with Bi-directional Data Bus
microprocessor
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
IN OUT SEL WR
WR_L
WE_L
CS_L
IOE_L
OE_L
DIO3
DIO2
DIO1
DIO0
36
Internal Address Decoding
The SRAM shown in the previous slides had 3
address lines and stored 8 words, requiring a
3-to-8 internal decoder.
Such a decoder requires eight AND gates,
with three inputs each, and three inversors.
Consider the HM628512 SRAM that has 19
address lines and stores 512K words. What size
internal decoder this chip requires?
A 19-to-512K decoder with 524288 AND gates,
each with 19 inputs?
37
Internal Address Decoding
To avoid such a complexity in the decoding
logic, all memories (EPROMs, SRAMs, and DRAMs)
use two-dimensional decoding which reduces the
decoder size to approximately the square root
of the number of addresses.
The memory cells are organized in a
two-dimensional array. Some address lines are
used to select a row and the others are used to
select a column. The cell selected by the whole
address is at the intersection of the row and the
column.
38
Static-RAM Read Timing
tAA (access time for address) how long it takes
to get stable output after a change in
address.
tACS (access time for chip select) how long it
takes to get stable output after CS is
asserted.
tOE (output enable time) how long it takes for
the three-state output buffers to leave the
high-impedance state when OE and CS are
both asserted.
tOZ (output-disable time) how long it takes for
the three-state output buffers to enter
high-impedance state after OE or CS are
negated.
tOH (output-hold time) how long the output data
remains valid after a change to the address
inputs.
39
Static-RAM Read Timing
stable
stable
stable
ADDR
CS_L
OE_L
tOE
valid
valid
valid
DOUT
WE_L HIGH
40
Static-RAM Write Timing
tAS (address setup time before write) all
address inputs must be stable at this time
before both CS and WE are asserted.
tAH(address hold time after write) all address
inputs must be held stable until this time
after CS or WE is negated.
tCSW (chip-select setup before end of write) CS
must be asserted at least this long before
the end of the write cycle.
tWP (write pulse width) WE must be asserted at
least this long to reliably latch data into
the selected cell.
tDS (data setup time before end of write) All of
the data inputs must be stable at this time
before the write cycle ends.
tDH (data hold time after the end of write) All
data inputs must be held stable until this
time after the write cycle ends.
41
Dynamic Memory Cell
An SRAM cell has a bi-stable latch that requires
from four to six transistors to be built.
42
Writing 1 in a Dynamic Memories
To store a 1 in this cell, a HIGH voltage is
placed on the bit line, causing the capacitor to
charge through the on transistor.
43
Writing 0 in a Dynamic Memories
To store a 0 in this cell, a LOW voltage is
placed on the bit line, causing the capacitor to
discharge through the on transistor.
44
Destructive Reads
To read the DRAM cell, the bit line is precharged
to a voltage halfway between HIGH and LOW,
and then the word line is set HIGH.
Depending on the charge in the capacitor, the
precharged bit line is pulled slightly
higher or lower. A sense amplifier detects this
small change and recovers a 1 or a 0.
45
Recovering from Destructive Reads
The read operation discharges the
capacitor. Therefore a read operation in a
dynamic memory must be immediately followed by a
write operation of the same value read to restore
the capacitor charges.
46
Forgetful Memories
The problem with this cell is that it is not
bi-stable only the state 0 can be kept
indefinitely, when the cell is in state 1, the
charge stored in the capacitor slowly dissipates
and the data is lost.
47
Refreshing the Memory
The solution is to periodically refresh the
memory cells by reading and writing back each one
of them.
48
Refreshing Frequency
Each dynamic RAM cell must be refreshed at about
every 4 miliseconds.
Some commercial DRAMs contain 256 megabits.
There would be no time for regular memory
accesses!!
How do we solve this problem?
49
Refreshing Memory
The DRAMs are organized in two dimensional
arrays, and a single refreshing operation can
refresh an entire row at a time.
Newer DRAMs have 4096 rows, but only need to
be refreshed every 64 miliseconds. Therefore they
require one refresh operation about every 15.6
?second. A refresh operation typically takes
100 nanoseconds. Therefore the memory is
available for regular accesses more than 99 of
the time.
50
Internal Structure of a 64K ? 1 DRAM
Row decoder
256 ? 256 array
row address
column address
A0-A7
control
Column latches, multiplexers, and demultiplexers
RAS_L
CAS_L
WE_L
latch, mux, and dmux control
DIN
DOUT
51
Read Cycle on an Asynchronous DRAM
52
Write Cycle on an Asynchronous DRAM
53
Improved DRAMs
Central Idea Each read to a DRAM actually reads
a complete row of bits or word line from the DRAM
core into an array of sense amps.
A traditional asynchronous DRAM interface then
selects a small number of these bits to
be delivered to the cache/microprocessor.
All the other bits already extracted from the
DRAM cells into the sense amps are wasted.
54
Fast Page Mode DRAMs
In a DRAM with Fast Page Mode, a page is defined
as all memory addresses that have the same row
address. To read in fast page mode, all the
steps from 1 to 7 of a standard read cycle are
performed. Then OE and CAS are switched high,
but RAS remains low. Then the steps 3 to 7
(providing a new column address, asserting CAS
and OE) are performed for each new memory
location to be read.
55
A Fast Page Mode Read Cycle on an Asynchronous
DRAM
56
Enhanced Data Output RAMs (EDO-RAM)
The process to read multiple locations in an
EDO-RAM is very similar to the Fast Page
Mode. The difference is that the output drivers
are not disabled when CAS goes high. This
distintion allows the data from the current read
cycle to be present at the outputs while the next
cycle begins. As a result, faster read cycle
times are allowed.
57
An Enhanced Data Output Read Cycle on an
Asynchronous DRAM
58
Synchronous DRAMs (SDRAM)
A Synchronous DRAM (SDRAM) has a clock input. It
operates in a similar fashion as the fast page
mode and EDO DRAM. However the consecutive data
is output synchronously on the falling/rising
edge of the clock, instead of on command by CAS.
How many data elements will be output (the length
of the burst) is programmable up to the maximum
size of the row.
The clock in an SDRAM typically runs one order of
magnitude faster than the access time
for individual accesses.
59
SDRAM Burst Read Cycle
60
DDR SDRAM
A Double Data Rate (DDR) SDRAM is an SDRAM that
allows data transfers both on the rising
and falling edge of the clock.
Thus the effective data transfer rate of a DDR
SDRAM is two times the data transfer rate of a
standard SDRAM with the same clock frequency.
61
The Rambus DRAM (RDRAM)
Multiple memory arrays (banks)
Rambus DRAMs are synchronous and transfer data
on both edges of the clock.
62
SDRAM Memory Systems
Complex circuits for RAS/CAS/OE.
Each DIMM is connected in parallel with the
memory controller. (DIMM Dual In-line
Memory Module)
Often requires buffering.
Needs the whole clock cycle to establish valid
data.
Making the bus wider is mechanically complicated.
63
RDRAM Memory Systems
64
Internal RDRAM Organization
65
SDRAM Protocol
66
RDRAM Protocol
67
Bank Conflicts
If two consecutive memory accesses are
accessing the same memory bank, there will be a
delay, or a bubble, in the response.
This delay happens because a memory device needs
time to recover after it completes a memory
access.
Thus the more banks a memory system has, the less
likely it will be to have delays caused by memory
bank conflicts.
68
SDRAM Bank Conflicts
69
RDRAM Banks ? SDRAM Banks
70
Dual In-line Memory Module (DIMM)
71
Rambus In-line Memory Module (RIMM)
72
A picture of RIMMs
73
Further Reading
To learn more about the differences between SDRAM
systems and Rambus DRAM systems for personal
computers, visit these websites
http//www.hardwarecentral.com/hardwarecentral/rev
iews/1787/1/ http//www.pcguide.com/ref/ram/tech_S
DRAM.htm
Crisp, Richard, Direct Rambus Technology The
New Main Memory Standard, IEEE Micro,
17(6) 18-28, Nov/Dec, 1997.