FPGA Technology Mapping: A Study of Optimality

1
FPGA Technology Mapping A Study of Optimality

• Andrew C. Ling M.A.Sc. Candidate University of
  Toronto
• Deshanand P. Singh Ph.D. Altera Corporation
• Professor Stephen D. Brown Altera Corporation
  Toronto University of Toronto

2
Goals

• Determine how good current FPGA LUT based
  technology mappers are in terms of
  area-optimality
• A. Farrahi and M. Sarrafzadeh (1994).Area
  problem shown to be NP-Hard

3
Method

• Take a set of benchmark circuits and technology
  map them to LUTs using one of the best existing
  LUT based technology mappers.
• Devise a resynthesis technique that is able to
  remove LUTs from these pre-existing technology
  mapped circuit.
• The more LUTs that can be removed, the farther
  the original technology mapping was from
  thearea-optimal solution.

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Resynthesis

• Attempt to map a cone with X LUTs to another cone
  with less than X LUTs

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Sliding Window Approach

• Resynthesize subcircuits
• Does not give the globally optimal solution
  however gives an indication of the area left on
  the table

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Background The Propositional Satisfiability
(SAT) problem

• Given a formula, f

• Defined over a set of variables, V

(a,b,c)
(C1,C2,C3)

• Comprised of a conjunction of clauses

• Each clause is a disjunction of literals of the
  variables V

SAT Seek an assignment of to the variables, V,
which sets expression to 1.
Example
abc1
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Construction of CNF

• T. Larrabee, Test pattern generation using
  Boolean satisfiability," TCAD, 1992 (Plaisted's
  and Greenbaum's encoding which is based on
  Tseitin's work)
• Creates a Characteristic Function for circuits

f(x2g) (x1g) (x2x1g)
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Construction of CNF (contd)
f AND (x2z1) (x1z1) (x2x1 z1)
f OR (x3g) (z1g) (x3z1 g)
f total fAND fOR (x2z1) (x1z1) (x2x1
z1) (x3g) (z1g) (x3z1 g)
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Formulating Resynthesis Problem
2-LUT
f
g
2-LUT
2-LUT
2-LUT
?
2-LUT

• Can function f be implemented in circuit g ?
• Does there exist a configuration to g such that
  for all inputs to g, f is equivalent to g

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Formulating Resynthesis Problem
2-LUT
f
g
2-LUT
2-LUT
2-LUT
?
2-LUT

• Derive characteristic function H for circuit g
• Replace all instances of g in H with f
• Hg/f (g f )
• f is equivalent to g

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Formulating Resynthesis Problem
2-LUT
f
g
2-LUT
2-LUT
2-LUT
?
2-LUT

• Does there exist a configuration to g such that
  for all inputs to g, f is equivalent to g ?

(g f )
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Formulating Resynthesis Problem
2-LUT
f
g
2-LUT
2-LUT
2-LUT
?
2-LUT

• Does there exist a configuration to g such that
  for all inputs to g, f is equivalent to g ?

A
E
l1lm x1xn(g f )
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Formulating Resynthesis Problem
2-LUT
f
g
2-LUT
2-LUT
2-LUT
SAT
2-LUT

• Express as a QBF with inputs (x1xn) and
  configuration bits (l1lm)
• l1lm x1xn (g f )
• Remove quantifiers to form a SAT problem(A.
  Biere. Resolve and Expand, SAT04)

A
E
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Resynthesis Structures Used

• Given a MFFC with 10 or less inputs and
  containing more than 3 LUTs, map it to

• Given a MFFC with 7 or less inputs and containing
  more than 2 LUTs, map it to

4-LUT
4-LUT
4-LUT
4-LUT
4-LUT
4-LUT
4-LUT
4-LUT
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Resynthesis Results, 4-LUTs
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Digital Logic Blocks with Tricks

• How intelligent are current technologymappers
  when it comes to some commondigital logic blocks?

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Techmap 41 MUX with 4-LUTs
a
b
out
c
d
s1
s0
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Techmap 41 MUX with 4-LUTs
a
b
s0
c
out
d
s1
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Techmap 41 MUX with 4-LUTs
a
s0
b
s0
c
out
d
s11
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Resuts using 4-LUTs
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Conclusions

• Current 4-LUT technology mappers still have room
  for improvement(5 on average, up to 10 for
  some circuits)
• For some logic blocks, current technology mappers
  have a very difficult time finding the optimal
  mapping to 4-LUTs (36 geomean, up to 67).
• Still has difficultly particularly for
  non-disjoint decomposition.

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Future Work

• Explore BDDs, QBF solvers and All Solution SAT
  solvers to speed up process
• If fast enough, this technique can be used asa
  valid resynthesis technique.
• Use Multiple Output Resynthesis
• Search for other optimal configurations ofcommon
  logic blocks, used in a caching schemefor
  resynthesis
• After technology mapping, search for digital
  logic blocks found in our cache, replace digital
  logic block with the cached optimal configuration

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Questions?