ELEE6374 Advanced Digital System Design

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ELEE6374 Advanced Digital System Design

• Lecture 6 Behavior Descriptions II
• 02/12/07

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Learning objectives

• Explain conditional statements using if and else.
• Describe multiway branching, using case, casex
  and casez statements.
• Understand looping statements such as for, while,
  repeat and forever.

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Activity Flow Control ( if else )

• if ( A lt B ) S_reg S 1
• if ( B lt C )
• if ( a gt b )
• begin
• end
• if ( A lt B ) P d
• else P k
• if ( A gt B ) P d
• else if ( A lt B ) P k
• else if
• else P Q

• Three types of if statements
• Syntax if ( expression ) statement else
  statement
• Multiple statements for a case must be grouped
  using begin and end.
• Value of expression
• 0, x or z gt false
• Non-zero number gt true

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Conditional Operator ( ? )

• Conditional operator can be applied in
• either continuous assignments
• or behavioral descriptions

• always _at_ ( posedge clock or negedge reset)
• if (reset 0) y_out0
• else y_out ( sel ) ? a b a b

always _at_ ( posedge clock or negedge reset) if
(reset 0) y_out0 else if (sel) y_out a
b else y_out a b
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The case Statement

• module mux4 ( a, b, c, d, select, yout )
• input a, b, c, d
• input 10 select
• output yout
• reg yout
• always _at_( a or b or c or d or select )
• begin
• case ( select )
• 0 yout a
• 1 yout b
• 2 yout c
• 3 yout d
• default yout 1bx
• endcase
• endmodule

• Case items are examined in order
• Exact match between case expression and case
  item, same bit-length.
• Case-item may be a single or a block statement.
• default is optional.
• caseendcase
• casex dont care bits with x and z
• casez dont care bits with z

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Expression Matching in case Construct

• always _at_ ( pulse )
• casez ( word )
• 8b0000????

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Loops

• repeat
• for loop
• while loop
• forever
• disable

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The repeat Loop

• word_address 0
• repeat ( memory_size )
• begin
• memory word_address 0
• word_address word_address 1
• end

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The for Loop

• reg 150 regA
• integer k
• for ( k 4 k k k 1 )
• begin
• regA k10 0
• regA k2 1
• end

Loop variables have to be either integer or reg
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The while Loop

• begin cnt1s
• reg 70 tmp
• cnt 0
• tmp regA
• while ( tmp )
• begin
• cnt cnt tmp0
• tmp tmp gtgt 1
• end
• end

Loop activities suspend external activities

• module sth ( externalSig )
• input externalSig
• always
• begin
• while ( externalSig )
• end
• endmodule

Replacement for while ?
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The disable Statement

• begin
• k 0
• for ( k 0 k lt 15 k k 1 )
• if ( word k 1 ) disable
• end

Terminate prematurely in a block of procedural
statements
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The forever Loop

• parameter half_cycle 50
• initial
• begin clock_loop
• clock 0
• forever
• begin
• half_cycle clock 1
• half_cycle clock 0
• end
• end
• initial
• 350 disable clock_loop

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always and forever
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Functions

• Defined within a module
• Implement only combinational behavior
• Compute and return a value for given parameters
• Have no timing/event control
• May call other functions, not itself
• Can be referenced anywhere an expression can
  exist
• Function name serves as the output variable
• Must have at least one input port

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Example of Function
module word_aligner (w_in, w_out) input 70
w_in output 70 w_out assign w_out
align (w_in) function 70 align
input 70 word begin align
word if (align ! 0) while
(align7 0) align align ltlt
1 end endfunction endmodule
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Example (1) 16-1 mux using function
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Examples (2) clock divider
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Example (3) 4-bit shift register
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Example (4) 74LS163
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Verilog model of 74LS163
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Simulation results