COE 308: Computer Architecture T032 Dr' Marwan AbuAmara

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COE 308 Computer Architecture (T032)Dr. Marwan
Abu-Amara

• Chapter 5 Pipelined Processor Design (cont.)

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Instruction Pipeline Hazards (cont.)

• Data Dependencies
• Data that the instruction uses depend on data
  created by other instructions
• 3 types
• True data dependency
• Antidependency
• Output dependency

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Instruction Pipeline Hazards (cont.)

• True Data Dependency
• ADD R3,R2,R1 R3 ? R2 R1
• SUB R4,R3,1 R4 ? R3 1
• Also called read-after-write hazard, and called
  flow dependencies
• Most troublesome to resolve in H/W
• Pipeline would need to be stalled until
  dependency is cleared (called also a bubble in
  the pipeline)

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Instruction Pipeline Hazards (cont.)
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Instruction Pipeline Hazards (cont.)

• Antidependency
• ADD R3,R2,R1 R3 ? R2 R1
• SUB R2,R3,1 R2 ? R3 1
• True dependency due to R3
• Antidependency happens if 2nd instruction alters
  R2 before it is read by 1st instruction (also
  called write-after-read hazard)
• As long as the read stage is before the write
  stage, then no issue
• Can happen if 1st instruction is stalled 2nd
  instruction is allowed to overtake 1st
  instruction in the pipeline

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Instruction Pipeline Hazards (cont.)

• Output Dependency
• ADD R3,R2,R1 R3 ? R2 R1
• SUB R2,R3,1 R2 ? R3 1
• ADD R3,R2,R5 R3 ? R2 R5
• True dependency antidependency can occur
• Dependency between 1st 3rd instructions R3
  must be produced by 1st instruction before 3rd
  instruction produces R3, so that 2nd instruction
  uses the proper value of R3 (i.e. dependency on
  the output of R3 between 1st 3rd instructions)
• Also called write-after-write hazard

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Detecting Data Hazards

• When data dependency occurs, there are 2 possible
  strategies
• Detect dependency then hold up pipeline until
  all instructions in pipeline are fully executed
• Allow only instructions that are independent to
  proceed in pipeline, delay instructions that
  are dependent on other instructions until they
  are executed
• Data dependency can be detected by considering
  read write operations on specific locations
  accessible by instructions

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Detecting Data Hazards (cont.)
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Detecting Data Hazards (cont.)

• Hazard occurs between instruction i instruction
  j if
• O(i) ? I(j) ? ? read-after-write hazard
• I(i) ? O(j) ? ? write-after-read hazard
• O(i) ? O(j) ? ? write-after-write hazard
• Where O(i) set of output locations altered by
  instruction i, and I(i) set of input locations
  read by instruction i

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Detecting Data Hazards (cont.)

• Example
• ADD R3,R2,R1 R3 ? R2 R1
• SUB R2,R3,1 R2 ? R3 1
• O(1) R3 , O(2) R2
• I(1) R1,R2, I(2) R3
• O(1) ? I(2) R3 ? ? read-after-write hazard
• I(1) ? O(2) R2 ? ? write-after-read hazard
• O(1) ? O(2) ? no
  write-after-write hazard

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Pipeline Interlocks

• A simple method to maintain proper read/write
  operations
• Use a 1-bit tag with each operand register
• 0 not valid (i.e. not ready)
• 1 valid (i.e. ready)
• Instruction that will write to register R
  examines the tag bit
• If tag 1
• Reset tag to 0 (i.e. R is not ready for other
  instructions)
• When instruction is done writing result to R, it
  sets tag of R to 1 (i.e. R is ready)

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Pipeline Interlocks (cont.)

• If tag 0 ? wait until it becomes 1
• Instruction that reads register R examines the
  tag bit
• If tag 1 ? read R
• If tag 0 ? wait until it becomes 1
• Example
• ADD R3,R4,4
• SUB R5,R3,8
• SUB R6,R3,12
• Instructions 2 3 wait until valid bit of R3 is
  set back to 1 before proceeding further in the
  pipeline

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Pipeline Interlocks (cont.)
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Forwarding

• Passing result of 1 instruction directly to
  another instruction to eliminate the use of
  intermediate storage locations
• Can be applied at compiler level to eliminate
  unnecessary references to memory locations
• Can also be applied at H/W level to eliminate
  pipeline cycles from reading registers that were
  updated in previous pipeline stage

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Forwarding (cont.)

• Compiler Directed Forwarding
• 3 types
• Store-fetch forwarding
• Fetch-fetch forwarding
• Store-store overwriting
• Store-fetch
• ST 200,R2 M200 ? R2
• LD R3,200 R3 ? M200
• ? ST 200,R2 M200 ? R2
• ADD R3,R2,R0 R3 ? R2 0

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Forwarding (cont.)

• Fetch-fetch
• LD R2,200 R2 ? M200
• LD R3,200 R3 ? M200
• ? LD R2,200 R2 ? M200
• ADD R3,R2,R0 R3 ? R2 0
• Store-store
• ST 200,R2 M200 ? R2
• ST 200,R3 M200 ? R3
• ? ST 200,R3 M200 ? R3

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Forwarding (cont.)

• Internal Forwarding
• Done in H/W not visible to programmer
• Example ADD R3,R2,R0
• SUB R4,R3,8