Seminar in ComputerAided Design of VLSI Hardware

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Seminar in Computer-Aided Design of VLSI Hardware

• Amir Rahat
• (Sorry its in English - my Intel habits)

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Agenda

• What is Seminar in Computer-Aided Design of VLSI
  Hardware?
• What is a Seminar?
• What is VLSI?
• What is Computer-Aided Design?
• What will you need to do in this Seminar, and how
  will it be graded?
• Schedule of Seminar meetings
• What you need to do this week
• Pick a paper, partner and date
• Introduction VLSI in a nutshell
• VLSI Design Validation

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A Seminar is a guided reading of recent research
papers

• Each week, a student presents one paper
  (approximately 75 minutes), and it will be
  discussed in class (approximately 15 minutes)
• I will be presenting in the first two weeks
• Presenter should prepare paper handouts, and
  explain in class
• What is the problem to be solved, and how does it
  fit in the design flow
• What is the solution proposed
• How are the software aspects addressed
• Was it used in a real design. And what were the
  results?
• Would you recommend it?
• At the end of the seminar, all participants
  should submit a short written review
• Of the papers presented in the seminar, and their
  main points (so take notes during the
  presentations!)
• The main goals of the Seminar
• Understand the state of the art in Computer-Aided
  Design
• Study useful techniques and learn how to apply
  them
• Practice self-learning, presentation and review
  skills

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What is VLSI?

• VLSI is the art of creating electrical components
  from very small transistors that are
  mass-produced as chemical layers
• 100 million transistors in a square inch
• VLSI includes two parts
• Creating a fabrication process that can create
  and connect very small transistors (not in the
  scope of this Seminar)
• Designing geometrical shapes that will create
  connected transistors using the process, such
  that together they implement the intended design
• VLSI Design is the process of creating these
  geometrical designs, or Layout
• The process is Top Down Starting with the
  abstract idea of what you want the component to
  do, and refining it in stages until you have
  Layout that is ready for fabrication (a stage
  called Tape Out)

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What is Computer-Aided Design?

• VLSI Design is a very complex process, requiring
  a lot of Software tools to help the various
  activities
• In general, SW tools are used for the following
  activities
• Capture Tools that help the designer write their
  ideas in a formal way
• Including text capture Graphical Capture
• Analysis Tools that help the designer understand
  the results of the design
• Including Verification (is it what I wanted?),
  Rule Checking (Does it follow the design
  rules?), Electrical behavior, etc.
• Synthesis Tools that automatically create the
  next level of refinement of the design
• Main synthesis tools create circuits from a logic
  design, and Layout from circuits

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What will you need to do in this Seminar?

• Read, understand, prepare and present one
  research paper
• Presentation should take about 75 minutes,
  followed by a 15 minutes discussion led by you
• Paper can be from my list, or a different paper
  you found
• All paper selections (on or off the list) have to
  be approved by me
• Attend other presentations (no less than 8) and
  be on time
• Submit a short written review of the papers
  presented in the seminar, and their main points
• About 2 pages of Word document or equivalent
• Preferably sent electronically (will be posted in
  the seminar web page)
• Individual work
• Submit within 3 weeks after the last Seminar
  meeting (currently scheduled for June 14).
• Learn, teach and have fun

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How will your work be graded?

• Grade Structure
• 65 for paper presentation
• 20 for class participation
• 100 Class participation requires at least two
  cases of notable contribution to the discussion
  in class, with deductions for more than 2
  absences and for being very late to class.
• 20 for homework
• 5 teacher's discretion
• Grades over 100 will be rounded to 100.
• Students will receive a short written review of
  their accomplishments, explaining how their
  grades were determined
• There will be no final exam, but there is a final
  review to be submitted
• Examples
• If you only attend your own presentation and it
  is perfect, you get 65
• If you do no homework, you cannot exceed 90
• If you get a balanced 90 on ALL your tasks, you
  can get a 100

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Schedule of Seminar meetings
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What you need to do this week

• Pick a paper and date
• In special cases, a paper can be presented by two
  students
• You may pick a paper not in my list
• Paper selection is subject to approval
• Contact me (details in the handouts) to reserve
  the date paper
• First come, first serve!
• The first presenter (15/3) gets special
  consideration due to limited time to prepare
• If we have more people than weeks you can either
  ask to join another presenter (if they agree) or
  we can schedule extra sessions that will not be
  mandatory for other people
• Start working on your paper!!!
• I will publish the schedule of papers, presenters
  dates as soon as possible

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Introduction to VLSI

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VLSI in a Nutshell

• This introduction will give a very short overview
  of VLSI
• For more details, refer to the Background
  textbooks in the handouts
• The basis for VLSI is the fabrication process
• Knowing how to mass-manufacture chips with 100s
  of millions of transistors on each one is the
  basis for the whole computer revolution from the
  1970s till today
• Next, we need to know how to design logic from
  these transistors
• Once the technology is available, we need a
  design flow to get from an idea (Lets open a
  start-up to sell Telepathic Internet) to a
  product
• Within the design flow, we identify where we can
  automate the work, and create CAD tools that
  assist in the design

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Moores Law in action
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Foil CreditIntel Corp.
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MOS TRANSITOR OPERATION

• NMOS Transistor Operation
• With the gate grounded (Fig. a)
• no inversion occurs
• no channel forms
• the NMOS transistor is off
• no current flows.
• With a positive voltage appliedto the gate
  (Fig. b)
• an n-channel bridge forms beneath the gate (the
  channel inverts) connecting the n-type source
  and drain together.
• The transistor is now on
• Electrons flow across the channel from source to
  drain, attracted by the positive drain voltage.
• (Note, conventional current flow is in the
  opposite direction.)

Foil Credit Intel Corp.
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The Fabrication Process Transistor
Cross-sectional View
OUT NOT A
Foil Credit Leor Nevo, Intel Corp.
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Abstract View of Process Layers
Silicon Oxide
Via 2
Metal 2
Via 1
Metal 1
Contact
Poly Silicon
Well Diffusion
Substrate
Foil Credit Intel Corp.
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Fab Terminology

• Lithography is the process which transfers the
  mask layer pattern to a light sensitive
  photoresist material which has been applied to
  the wafers.

Photoresist
Metal 1
ILD0 Oxide
Photoresist
Metal 1
ILD0 Oxide
Foil Credit Intel Corp.
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Fab Terminology

• Etch is the process which transfers the
  photoresist pattern to an underlying nitride,
  oxide, silicon, poly or metal layer.

Photoresist
Metal 1
ILD0 Oxide
Metal 1
ILD0 Oxide
Foil Credit Intel Corp.
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Fab Terminology

• Polish is the process that chemically and
  mechanically planarizes oxide, nitride, or
  tungsten layers.

ILD1 Oxide
Metal 1
ILD0 Oxide
ILD1 Oxide
Metal 1
ILD0 Oxide
Foil Credit Intel Corp.
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Some pictures
Metal 2
Metal 2
Via 1
Metal 1
Diffusion Contact
Foil Credit Intel Corp.
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From Transistor to Logic - NAND
VCC
VCC
A
B
OUT
A
B
VSS
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The development process
The Design process
implement,
Specify,
Check,
produce
-Volume Mfg.
Definition
1st Silicon

• Do it right the first time - iterations increase
  cost and effort
• Overall trend from ART to ENGINEERING DISCIPLINE
  
• Issues complexity, correctness, productivity

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The Simple Design Flow Chip Definition

• Once we have a fabrication process a need for
  an electrical component, we can start a VLSI
  Design process
• For simplicity, we assume a Digital, Synchronous
  design
• First, Marketing defines what the component must
  do
• Functionality (how should it behave)
• Cost (translated into component size)
• Speed (how fast is the clock, and how many clocks
  per user-visible activity)
• Power consumption (impacts battery life and
  cooling)
• Reliability (how may years will it work before
  something burns out)
• Next, an Architect defines the functionality of
  the chip in detail
• E.g., how a floating point is computed, how a
  Cellular protocol is implemented, etc.
• Also outlines the main partitions of the
  component and their interactions
• These can be units inside the component,
  interacting components on a board, or SW
  implementations

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The Simple Design Flow Chip Implementation

• A Logic Designer implements the HW units in a
  Hardware Definition Language (HDL), creating a
  Register Transfer Level (RTL) model of the unit
• This should be the exact behavior of the unit, in
  terms of its registers
• Syntactically, this looks like a SW programming
  language
• Semantically, all statements in a block are
  executed in parallel
• The RTL can be analyzed for adherence to RTL
  Design Rules, often with an RTL analysis CAD tool
• The RTL is implemented as a set of interconnected
  gates
• This is often done with a Synthesis CAD tool
• The gates can be analyzed to determine electrical
  properties and adherence to circuit design rules,
  often with Analysis CAD tools
• A Physical Designer implements the Gates as
  Layout
• This is often done with a Layout Synthesis CAD
  tool
• The layout can be analyzed to determine physical
  properties and adherence to layout design rules,
  often with Analysis CAD tools

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The Simple Design Flow Chip Verification

• Every step of the design process has to be
  verified
• Is it an accurate implementation of the previous
  level?
• Does it meet the requirements of Marketing?
• Early capture of functional bugs is critical, due
  to the cost of late fixes of closed designs -
  initial fabrication can take up to 2 months, and
  user detection of bugs is even costlier! The goal
  is first-time functional silicon.

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The Simple Design Flow Chip Verification (cont.)

• RTL Verification checks adherence to the
  architectural specification
• Does the component behave as intended, and in the
  number of clock cycles specified?
• Main techniques are simulation of the RTL
  (compared with expected results or with a
  separate correct model like a C program or a
  previous HW component), and formal verification
  of properties (a very new and limited technique).
  All require CAD assistance.
• Circuit Verification checks adherence to RTL and
  to the electrical specifications like timing,
  power, reliability etc.
• Main techniques are simulation (to check
  functional or electrical behavior), formal
  verification of functional equivalence, and
  static analysis of electrical properties. All
  require CAD assistance.
• All circuits at this stage are estimated, since
  some properties can only be determined after
  Layout is done!

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The Simple Design Flow Chip Verification (cont.)

• Layout Verification checks adherence to the
  circuit, and adherence to the layout
  specifications (e.g., overall shape)
• Main technique is extraction of electrical
  properties from the layout, and formal
  equivalence checking against the circuit, as well
  as geometric rule checking. These require CAD
  assistance
• Post-layout circuit Verification checks the
  actual circuits that were implemented for
  adherence to the electrical specifications
• E.g., the resistance of a connection between two
  transistors depends on the length of the wire,
  which depends on their actual placement in the
  layout
• The main technique is extraction of the
  parasitic properties from the layout, adding
  them to the original circuit and repeating the
  stage of circuit verification relating to
  electrical properties (parasitics do not change
  the functionality!)
• Parasitics The actual resistors and capacitors
  that are created unintentionally when the layout
  is designed. E.g., resistance of a connection or
  capacitance between two wires.

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The Major Design Problems

• Enable maximal complexity with high productivity
• Ensure design correctness
• Make the right trade-offs

Complexity
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Complexity

• Principles for handling complexity
• Hierarchy divide and conquer (encapsulation,
  modularity)
• Regularity Multiple instances
• Abstraction show relevant features without
  associated details
• Design Methodology

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Future Technology characteristics (ITRS 99 -
predictions for MPU chips)
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Where can CAD help?

• Digital hardware modelingmodeling structure and
  behavior logic networks connectivity
  data-structures HDLs RTL models
• Dynamic verification (logic simulators) modeling
  of logic values and timing how simulators are
  built simulation algorithms
• Static verificationAdvantages of non-simulation
  methods equivalence checking advanced Boolean
  algebra
• Binary Decision Diagrams and formal
  verificationstructure and operation of the BDD
  data-structure logic and state-machine
  equivalence checking
• Logic synthesis2-level and multilevel
  minimization, exact vs. heuristic methods,
  cell-library mapping
• Layout synthesislayout models partitioning
  floorplanning placement routing compaction
• Static timing analysisdelay modeling critical
  path analysis false path elimination time
  borrowing interconnect effects
• Performance-driven synthesisconvergence problem
  retiming logic transformations device sizing,
  layout synthesis for speed

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Can this flow be more complex?

• Yes
• We skipped over many activities that would make
  this picture more complex
• Testability A logic design verification
  activity that ensures that the we will be able to
  test each product as it is created, to find
  faulty units before they are sold
• Reliability Signal Integrity A circuit design
  verification activity that ensures the data is
  transferred across lines correctly over years of
  usage
• Standard-cell design The basis for all synthesis
  is a library of well-analyzed perfect cells
  that are instantiated as needed, requiring
  circuit layout design and analysis
• Clock design The clock signal timing is both
  crucial and overloaded, so special circuit and
  layout design techniques are required
• and more

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The Simple Design Flow Fully Automated (example)
Verification
Tape out
Redo
(In this flow, all circuit verification is done
after Layout, and Extraction includes Layout
verification
Redo
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What did we learn?

• The fabrication process requires design of the
  geometrical shapes that make up transistors
  connections
• The VLSI design flow works in stages, and each
  stage has to be verified
• Architecture
• RTL
• Circuit
• Layout (and Post-Layout Circuit verification)
• Most activities require CAD tools
• Simulators
• Formal verification (mostly equivalence checkers)
• Synthesis tools
• Analysis tools
• There is still a lot of work to be done the
  flow is difficult, and takes many people and a
  lot of time to go thru
• No pushbutton tapeout yet