CMOS Inverter and Logics

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CMOS Inverter and Logics

• Dr. T.Y. Chang
• NTHU EE
• Oct. 4 , 2005

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Contents

• PMOS
• CMOS Inverter
• CMOS Logic
• Text Book D.A. Neamen, Electronic Circuits
  Analysis And Design, 2nd ed. Chapter 16.

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PMOS

VTP)2
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CMOS Inverter
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Current-Voltage of NMOS and PMOS
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NMOS and PMOS off

• ViltVTN or VigtVDDVTP

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VTN lt ViltVDDVTP
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Vi-Vo of CMOS Inverter
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VDD of CMOS Inverter
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Relations of Current and Vi
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Output Switching
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Noise Margins

• VIL IN,SatIP,NonSat d/dvi
• VIH IN,NonSatIP,Sat d/dvi

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CMOS Logic

• Function
• Ratioless
• But ratio will affect speed

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CMOS NOR Gate
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CMOS NAND Gate
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NOR as inverter
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Example 16.2

• Design the CMOS with function of
• F(ABC (DE))
• Sol.
• Design NMOS first
• AND Series connection
• OR Parallel connection
• Design PMOS
• Dual of NMOS circuit
• Series -gt Parallel
• Parallel -gt Series

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Design the NMOS Logic

• F(ABC (DE))
• AB in series
• DE in parallel
• C in series with (DE)
• AB in series with C(DE)

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Design the PMOS Logic

• Dual of NMOS
• Series -gt Parallel
• Parallel -gt Series
• Exception
• Same function if 0 ? 1
• Then Same connections

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Full adder
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Implementation
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Speed

• ?VIOt/CL
• CL ?N(WL)L (WL)D
• IO ? (W/L)L or (W/L)D
• t CL?V/IO
• t?N(WL)L (WL)D ?V/(W/L)(L or D)

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Problem

• Design a Full adder cell and compare with Fig.
  16.77 in area and delay by transistor count.