Electronic System Design Group CMS Tracker FED

1
Electronic System Design GroupCMS Tracker FED

• Presentation to CALICE
• 22nd October 2002
• 1300 - 1700
• UCL

2
CMS Tracker FEDFunctionality
5V
3.3V
Run/Halt
Config E2PROM
Id E2 Prom
1.5V
5V
3.3V
1.5V
1
0V
3.3V
Compact Flash
1
Test Connector
1
VME
LEDs
4x Prog Delay
1
Dual ADC
12x Opto Rx
1
Power Good
VME64x Interface FPGA
FPGA
Synch Processing
Boundary Scan
System ACE
Buffer Jumper Matrix
-5V
ASIC
12x trim dac
Vref
VME
FE 1
PD Array
3
6
4x Prog Delay
12V
12
Dual ADC
LEDs
Temp Sense
5V
Front End FPGA
3.3V
FPGA
Temp Sense
Clock Control Data
2.5V
1.5V
2.5V
0V
LEDs
2
1.5V
QDR SSRAM
-5.0V
spare
Over temp
LEDs
TTS
TTCrx
TTC
DAQ
Readout Synch Control
ASIC
FLT
LEDs
EMU
FSYNC
Spare
Process
Back End FPGA
LEDs
Transfer
VME
Temp Sense
43
85
22
Readout
Clock Control Data
4x Prog Delay
3.3V
1.5V
Dual ADC
8
Busy
12x Opto Rx
8
LEDs
error
FPGA
halted
Synch Processing
ASIC
12x trim dac
Vref
FE 8
PD Array
24
4x Prog Delay
48
5.0 V
96
E-Fuse Hot swap DC-DC
3.3 V
Front End FPGA
Dual ADC
FPGA
2.5V
Temp Sense
1.5V
-5.0V
extract
Hot swap cycle
SW
Live extract request
SW
3
FEDv1 Board Layout Primary Side
4
FEDv1 Board Layout Secondary Side

• View Through board