Digital System Design Using

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• Digital System Design Using
• VHDL
• for
• VI Sem (ECE,TCE)
• By
• K.S.GURUMURTHY M.E, PhD
• UVCE, Bangalore University
• Bangalore-1
• drksgurumurthy_at_gmail.com

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AGENDA

• FPGA-Programming Technology

• Anti fuse, EPROM

• XC3020 FPGA

• CLB-Details

• I/O BLOCK

• XC4000

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TYPES OF FPGAs

• Depend on the programming Technology

• Static RAM BasedXilinx

Static RAM..Stored program as long power is
there

• EPROM Based ..Altera

• ANTIFUSE Based .Actel

EPROM..Stored program non-volatile
Antifuse. One time programmable
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Types of FPGAs
CONFIGURATION MEMORY CELL
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Antifuse Technology
Actels Antifuse
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TYPES OF FPGAs (contd..)

polysilicon
Before programming R VERY HIGH After
Programming R 100 Ohms
ONO
Diffusion
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EPROM PROGRAMMING
VGS
VGS
VGS
VGS
VDS
VPP
VDS
VDS
IDS
IDS
b) Hot electron Injection
c) Device is OFF with Vt1gt Vt
d) Device is ON with Vt
a) Device is ON with Vt
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XILINX-3000 SEIRE FPGAs
Lay out part of PLC Array

• Xilinx XC3020 LCA
• Basic Structure
• Interior array of 64 CLBs
• (Some combinational logic 2 D flip-flops)
• Ring of 64 input-output Interface Blocks
• The Interconnections

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8x864 CLBs
64 I/Os
256F/Fs
16 Horizontal Long lines
14,779 Configuration Data bits
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DI
0
DATA IN
MUX
D
Q
F
1
Logic variables
DI
RD
X
QX
G
Combinational Block
QX
F
F
A
CLB OUTPUTS
M
M M
B
C
G
G
D
Y
M M
E
QY
F
QY
DI
0
D
Q
MUX
M
G
1
EC
RD
Xilinx 3000 Series CLB
1
(ENABLE)
K
M
M
0
O
RD
M
RG
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Combinational Function Block

• Contains RAM memory cell

• Can be programmed to realise any function of
• 5 variables or any 2 functions of 4 variables

• The functions are stored in truth table

• Three modes of operation for this block

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A
ABQX.E
Any Function Of 4 Variables
B
QX
F
QY
C
D
E
2 Functions of 4 variables
Any Function Of 4 Variables
QX
QY
G
ACQY.D
FG MODE LOGIC OPTION
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F MODE Logic Option
A
Any Function Of 5 Variables
B
QX
F/G
QY
C
D
E
One Function of 5 variables
Ex FGABCDE.AND gate FGAE xor B xor
C xor D xor E
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FGM MODE LOGIC OPTION
A
Any Function Of 4 Variables
B
QX
QY
C
D
E
M U X
F/
G
Any Function Of 4 Variables
QX
QY
E is control input to select one of 4 variable
functions
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XILINX 3000 SERIES I/O BLOCK
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XILINX-3000 SERIES FPGA (contd..)
PROGRAMMABLE INTERCONNECTS

• GENRAL PURPOSE
• DIRECT INTERCONNECTIONS BETWEEN ADJACENT
• CELLS
• VERTICAL HORIZONTAL LONG LINES

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GENERAL PURPOSE INTERCONNECTS
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DIRECT INTERCONECTS BETWEEN ADJACENT CLBs
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VERTICAL AND HORIZONTAL LONG LINES
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4000 series CLB
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XC4000 DEDICATED CARRY LOGIC
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4000 SERIES I/O BLOCK
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Designing with FPGAs
Steps

• Draw a Block diagram of the digital system.

• Construct the SM chart for the same.

• Write the corresponding VHDL code for the chart

• Simulate and debug the VHDL code. Make necessary
  changes

• Synthesise the code to generate the net list.

• Run a partitioning program.This will map the
  logic on to CLB.

• Run the automatic place route program

• Run a program to generate the bit pattern
  needed for
• programming

• Down load the program to the FPGA

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XILINX DESIGN FLOW
Start
Prelayout simulation
Design entry
P R
To xnf
Back annotated Netlist with delays
.XNF Net list
Netlist with Unit delays
Netlist without delays
.XNF net list
Create Programming file
Make bits
Partitioning into CLBs
xmake
.BIT file
10110.
.LCA Net list
To FPGA or EPROM
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EPROM Connections for LCA Initialisation
DATA
F P G A
EPROM (contains Configur- ationion Data)
ADDRESS
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