Y Counter

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(No Transcript)
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MOUSE
Y Counter
The movement of the Mouse increments or
decrements the X and Y counters
X counter
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MOUSE
Y Counter
The movement of the Mouse increments or
decrements the X and Y counters.
If the location of the cursor is updated 20 times
per second it appears smooth to a human.
X counter
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MOUSE
Y Counter
The movement of the Mouse increments or
decrements the X and Y counters.
If the location of the cursor is updated 20 times
per second it appears smooth to a human.
X counter
GIVEN

• Poll at 40 times per second.
• 2. Polling I/O routine takes 800 clock cycles
• Each counter is 2 Bytes, Sample is 1 Word
• Clock Rate is 500 MHz

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MOUSE
GIVEN

• Poll at 40 times per second.
• 2. Polling I/O routine takes 800 clock cycles
• Each counter is 2 Bytes, Sample is 1 Word
• Clock Rate is 500 MHz

Processor Usage? Each Polling Cycle is 1/40
sec Number of clock cycles each polling cycle
500x106 clock cycles/sec 1/40 sec 12.5 x
106
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MOUSE
GIVEN

• Poll at 40 times per second.
• 2. Polling I/O routine takes 800 clock cycles
• Each counter is 2 Bytes, Sample is 1 Word
• Clock Rate is 500 MHz

Processor Usage? Each Polling Cycle is 1/40
sec Number of clock cycles each polling cycle
500x106 clock cycles/sec 1/40
sec 12.5 x 106 Processor Usage 800
64 x 10-6 0.0064
12.5 x 106
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MOUSE
GIVEN

• Poll at 40 times per second.
• 2. Polling I/O routine takes 800 clock cycles
• Each counter is 2 Bytes, Sample is 1 Word
• Clock Rate is 500 MHz

Processor Usage? Each Polling Cycle is 1/40
sec Number of clock cycles each polling cycle
500x106 clock cycles/sec 1/40
sec 12.5 x 106 Processor Usage 500
40 x 10-6 0.004
12.5 x 106 Transfer Rate 4 bytes
40 times/ sec 160 bytes / sec
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HARD DRIVE
Platters 6 Surfaces and Heads
Tracks or Cylinders
Sectors
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HARD DRIVE
Seek Time- Move Head to Track - Min, Max, Ave.
Platters 6 Surfaces and Heads
Tracks or Cylinders
Sectors
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HARD DRIVE
Seek Time- Move Head to Track - Min, Max, Ave.
Platters 6 Surfaces and Heads
Tracks or Cylinders
Rotational latency Time for the sector to
rotate to the Head Average is ½ rotation time
Sectors
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HARD DRIVE
Given Average Seek Time 10 ms Rotational
speed 5400 RPM Sector size 512
bytes Data Rate 5 MBpsec What is the average
transfer rate?
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HARD DRIVE
Seek Time- Move Head to Track - Min, Max, Ave.
Platters 6 Surfaces and Heads
Tracks or Cylinders
Rotational latency Time for the sector to
rotate to the Head Average is ½ rotation time
Sectors
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HARD DRIVE
Given Average Seek Time 10 ms Rotational
speed 5400 RPM Sector size 512
bytes Data Rate 5 MBps What is the average
transfer rate from the disk? Time to transfer a
sector 10 ms ½ (60 sec/min) 512 bytes
5400 rev/min 5 x 106
bytes/sec 10 5.56 0.102 ms 15.67 ms
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HARD DRIVE
Given Average Seek Time 10 ms Rotational
speed 5400 RPM Sector size 512
bytes Data Rate 5 MBps What is the average
transfer rate from the disk? Time to transfer a
sector 10 ms ½ (60 sec/min) 512 bytes
5400 rev/min 5 x 106
bytes/sec 10 5.56 0.102 ms 15.67
ms Average transfer rate 512 bytes 32.7
KBps from the disk 15.67ms
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HARD DRIVE
What is the time to transfer 4 KB from the disk
under DMA? Given 1. OS requires 1000 clock
cycles for initial set up and 500 clock cycles
to handle completion interrupt 2. Clock is
500 Mhz 3. Average transfer rate from the disk
is 32.7 KBps
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HARD DRIVE
What is the time to transfer 4 KB from the disk
under DMA? Given 1. OS requires 1000 clock
cycles for initial set up and 500 clock cycles
to handle completion interrupt 2. Clock is
500 MHz 3. Average transfer rate from the disk
is 32.7 KBps Transfer time for 4 KB 1000
clocks 4 K B 500 clocks
500 MHz 32.7 KBps 500
MHz
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HARD DRIVE
What is the time to transfer 4 KB from the disk
under DMA? Given 1. OS requires 1000 clock
cycles for initial set up and 500 clock cycles
to handle completion interrupt 2. Clock is
500 MHz 3. Average transfer rate from the disk
is 32.7 KBps Transfer time for 4 KB 1000
clocks 4 K B 500 clocks
500 MHz 32.7 KBps 500
MHz 0.002 ms 122.32 ms
0.001 ms
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HARD DRIVE
What is the Processor usage for this transfer?
Given 1. OS requires 1000 clock cycles for
initial set up and 500 clock cycles to handle
completion interrupt 2. Clock is 500 MHz
3. Average transfer rate from the disk is 32.7
KBps 4. Time to transfer 4 KB 122.32 ms
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HARD DRIVE
What is the Processor usage for this transfer?
Given 1. OS requires 1000 clock cycles for
initial set up and 500 clock cycles to handle
completion interrupt 2. Clock is 500 MHz
3. Average transfer rate from the disk is 32.7
KBps 4. Time to transfer 4 KB 122.32
ms Processor time 1000 500 clocks
0.003 ms 500
MHz
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HARD DRIVE
What is the Processor usage for this transfer?
Given 1. OS requires 1000 clock cycles for
initial set up and 500 clock cycles to handle
completion interrupt 2. Clock is 500 MHz
3. Average transfer rate from the disk is 32.7
KBps 4. Time to transfer 4 KB 122.32
ms Processor time 1000 500 clocks
0.003 ms 500
MHz Processor usage 0.003 0.0025
122.32
Assuming no memory contention
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A floppy disk transfers data to the processor in
32 bit units and has a data rate of 40,000 bytes
per sec. No data transfers can be missed.
Consider a computer with a 900 MHz clock rate and
a polling loop of 500 clock cycles that includes
the cycles to transfer a 32 bit unit. What
is the required polling rate to not miss any
data?
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A floppy disk transfers data to the processor in
32 bit units and has a data rate of 40,000 bytes
per sec. No data transfers can be missed.
Consider a computer with a 900 MHz clock rate and
a polling loop of 500 clock cycles that includes
the cycles to transfer a 32 bit unit. What
is the required polling rate to not miss any
data? Polling Rate 40,000 bytes/sec 8
bits/byte 1 32 bits/unit
10,000 units /sec
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What is the Processor Usage? Polling period
1/10,000 0.1 msec
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What is the Processor Usage? Polling period
1/10,000 0.1 msec Processing time per poll
500 clock cycles 900 MHz 0.555
microsec
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What is the Processor Usage? Polling period
1/10,000 0.1 msec Processing time per poll
500 clock cycles 900 MHz 0.555
microsec Processor usage 0.555microsec
0.555 microsec 0.1 msec 100
microsec
0.555
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Consider a interrupt driven I/O instead of
polling with a interrupt routine of 750 clock
cycles that includes the cycles to transfer a 32
bit unit each interrupt. If the floppy disk is
active transferring data 15 of the time, what is
the Processor Usage?
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Consider a interrupt driven I/O instead of
polling with a interrupt routine of 750 clock
cycles that includes the cycles to transfer a 32
bit unit each interrupt. If the floppy disk is
active transferring data 15 of the time, what is
the Processor Usage?
Processing time each interrupt 750 clock
cycles 900 Mhz
0.833 microsec Interrupt period 32 bits/
unit during transfer
8 bits/byte 40,000 bytes/sec 0.1
x 10-3 sec/transfer
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Consider a interrupt driven I/O instead of
polling with a interrupt routine of 750 clock
cycles that includes the cycles to transfer a 32
bit unit each interrupt. If the floppy disk is
active transferring data 15 of the time, what is
the Processor Usage?
Processing time each interrupt 750 clock
cycles 900 Mhz
0.833 microsec Interrupt period 32 bits/
unit during transfer
8 bits/byte 40,000 bytes/sec 0.1
x 10-3 sec/transfer Processor usage 15
0.833x10-6 0.125
0.1 x 10-3
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Machine Instructions ( MIPS) take five steps 1.
Fetch instruction from memory 2. Read
registers and decode operation 3. Execute the
operation or calculate an address 4. Access an
operand in data memory 5. Write the result in a
register
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Machine Instructions ( MIPS) take five steps 1.
Fetch instruction from memory Instruction
Cache PC 2. Read registers and decode
operation 3. Execute the operation or calculate
an address 4. Access an operand in data
memory 5. Write the result in a register
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Machine Instructions ( MIPS) take five steps 1.
Fetch instruction from memory Instruction
Cache PC 2. Read registers and decode
operation Register File 3. Execute the
operation or calculate an address 4. Access an
operand in data memory 5. Write the result in a
register
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Machine Instructions ( MIPS) take five steps 1.
Fetch instruction from memory Instruction
Cache PC 2. Read registers and decode
operation Register File 3. Execute the
operation or calculate an address ALU 4.
Access an operand in data memory 5. Write the
result in a register
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Machine Instructions ( MIPS) take five steps 1.
Fetch instruction from memory Instruction
Cache PC 2. Read registers and decode
operation Register File 3. Execute the
operation or calculate an address ALU 4.
Access an operand in data memory Data Cache 5.
Write the result in a register
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Machine Instructions ( MIPS) take five steps 1.
Fetch instruction from memory Instruction
Cache PC 2. Read registers and decode
operation Register File 3. Execute the
operation or calculate an address ALU 4.
Access an operand in data memory Data Cache 5.
Write the result in a register Register File
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Machine Instructions ( MIPS) take five steps 1.
Fetch instruction from memory Instruction
Cache PC 2. Read registers and decode
operation Register File 3. Execute the
operation or calculate an address ALU 4.
Access an operand in data memory Data Cache 5.
Write the result in a register Register
File Pipelining is overlapping these stages of
execution
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time ns 2 4 6
8 10 12
IF Reg ALU Mem Reg
Instr 1
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time ns 2 4 6
8 10 12
IF Reg ALU Mem Reg
Instr 1
IF Reg ALU Mem Reg
Instr 2
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time ns 2 4 6
8 10 12
IF Reg ALU Mem Reg
Instr 1
IF Reg ALU Mem Reg
Instr 2
IF Reg ALU Mem Reg
Instr 3
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time ns 2 4 6
8 10 12
IF Reg ALU Mem Reg
Instr 1
IF Reg ALU Mem Reg
Instr 2
IF Reg ALU Mem Reg
Instr 3
IF Reg ALU Mem Reg
Instr 4
IF Reg ALU Mem Reg
Instr 5
Pipelining increases instruction throughput
approaching the number of stages. Must add
PIPELINE REGISTERS
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Pipeline Hazards Situations occur when the next
instruction cannot be overlapped
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Pipeline Hazards Situations occur when the next
instruction cannot be overlapped Structural
Hazards occur when the hardware cannot support
the combination of instructions
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time ns 2 4 6
8 10 12
IF Reg ALU Mem Reg
Instr 1
IF Reg ALU Mem Reg
Instr 2
IF Reg ALU Mem Reg
Instr 3
IF Reg ALU Mem Reg
Instr 4
IF Reg ALU Mem Reg
Instr 5
MIPS instruction set was designed for pipelining
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time ns 2 4 6
8 10 12
IF Reg ALU Mem Reg
Instr 1
IF Reg ALU Mem Reg
Instr 2
IF Reg ALU Mem Reg
Instr 3
IF Reg ALU Mem Reg
Instr 4
IF Reg ALU Mem Reg
Instr 5
MIPS instruction set was designed for
pipelining If cannot overlap due to hardware
constraints?
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Pipeline Hazards Situations occur when the next
instruction cannot be overlapped Structural
Hazards occur when the hardware cannot support
the combination of instructions 1. Design ISA
for pipelining 2. Stall to clear
( Delay)
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Pipeline Hazards Situations occur when the next
instruction cannot be overlapped Structural
Hazards occur when the hardware cannot support
the combination of instructions 1. Design ISA
for pipelining 2. Stall to clear (
Delay) Control Hazards occur when a decision
needs to be made while others are executing - a
branch instruction
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time ns 2 4 6
8 10 12
IF Reg ALU Mem Reg
instr 1
IF Reg ALU Mem Reg
bne 4, 5, 20
IF Reg ALU Mem Reg
add 1, 2, 3
Execute the next instruction or take the branch?
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Control Hazards occur when a decision needs to be
made while others are executing - a branch
instruction 1. Stall until branch can be
resolved Some compilers can fill the delays
with useful instructions.
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Control Hazards occur when a decision needs to be
made while others are executing - a branch
instruction 1. Stall until branch can be
resolved Some compilers can fill the delays
with useful instructions. 2. Predict the
branch decision. If correct, then full
speed If wrong, nullify instructions following
the wrong branch and restart the pipeline at
the correct address
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Pipeline Hazards Situations occur when the next
instruction cannot be overlapped Structural
Hazards occur when the hardware cannot support
the combination of instructions Control Hazards
occur when a decision needs to be made while
others are executing - a branch instruction Data
Hazards occur when an instruction depends on
the results of a previous instruction still in
the pipeline.
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time ns 2 4 6
8 10 12
IF Reg ALU Mem Reg
Instr 1
IF Reg ALU Mem Reg
lw t1, 0(t0)
IF Reg ALU Mem Reg
add s2, s1, t1
The data t1 is not available to start the add
operation.
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time ns 2 4 6
8 10 12
IF Reg ALU Mem Reg
Instr 1
IF Reg ALU Mem Reg
lw t1, 0(t0)
IF Reg ALU Mem Reg
add s2, s1, t1
The data t1 is not available to start the add
operation. Stall until available or Reorder by
compiler
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time ns 2 4 6
8 10 12
IF Reg ALU Mem Reg
IF Reg ALU Mem Reg
lw t1, 0(t0)
add s2, s1, t1
IF Reg ALU Mem Reg
Forwarding is passing a needed result from an
earlier instruction to a later instruction in the
pipeline.
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Data Hazards occur when an instruction depends on
the results of a previous instruction still in
the pipeline. 1. Stall 2. Reorder 3.
Forwarding combined with stall and reorder
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Review for Exam III Chapter 7 Memory
Hierarchy Organization and operation of
Caches Direct, 2-way and 4-way associative
with multiword blocks. Memory Organizations
interfacing with Cache
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Review for Exam III Chapter 7 Memory
Hierarchy Organization and operation of
Caches Direct, 2-way, 4-way and Fully
associative with multiword blocks. Memory
Organizations interfacing with Cache Cache
Performance Measures Ave Memory Access Time,
Hit Rate, Miss Rate, Miss Penalty, Effective
CPI
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Review for Exam III Chapter 7 Memory
Hierarchy Organization and operation of
Caches Direct, 2-way and 4-way associative
with multiword blocks. Memory Organizations
interfacing with Cache Cache Performance
Measures Ave Memory Access Time, Hit Rate,
Miss Rate, Miss Penalty, Effective
CPI Organization and operation of Virtual
Memory Page Tables, TLB, TLB Miss, Page Fault
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Review for Exam III Chapter 8 Input /
Output I/O Busses
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Review for Exam III Chapter 8 Input /
Output I/O Busses Polling, Interrupt Driven, DMA
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Review for Exam III Chapter 8 Input /
Output I/O Busses Polling, Interrupt Driven,
DMA Performance I/O Rates, Processor Usage