Lecture 21 MOS Amplifier Compensation

1
Lecture 21MOS Amplifier Compensation

• Switched-Capacitor Filter Using OPAMP
• OPAMP Performance Parameters
• Negative Feedback
• OPAMP design and compensation
• Miller Approximation
• Summary
• Reading Ch. 6, 8, 9 of Gray, Hurst, Lewis, and
  Mayer

• Michael L. Bushnell
• CAIP Center and WINLAB
• ECE Dept., Rutgers U., Piscataway, NJ

2
OPAMP Design and Compensation

• Requirements
• Internal amplifiers load on amplifier is
  well-defined often purely capacitive (a few
  pFs)
• Output buffers Only a few amplifiers must drive
  an off-chip signal where capacitive and resistive
  loads are significant and variable

3
Widely-Used Switched-Capacitor Integrator
4
Timing Behavior
5
Switched-Capacitor Integrator

• Integrator frequency response is insensitive to
  parasitic Cs present on both terminals of
  monolithic capacitors
• Synthesis of filter frequency is straightforward
• When f1 high
• M1 M3 in linear region charge sampling
  capacitor CS to vi
• f1 low, f2 high
• M1 M3 turn off, M2 M4 turn on
• CS connected between OPAMP summing node ground
• Then, OPAMP drives summing node back to ground

6
Equivalent Circuit
7
Circuit Behavior

• Causes charge stored on CS to be dumped into CI,
  because after transient, CS voltage is driven to
  0
• Q CS vi
• DQCf Q
• Dv0 DQCf CS vi
• CI CI
• nT and (n 1) T defined as in switched-C circuit
  so
• v0(n 1) v0n CS vi
• CI
• Delaying a signal by a clock period T is
  equivalent to multiplication by e-jwT in
  frequency domain

)
(
8
Frequency Domain Behavior
)
(

• v0 (jw) v0 (jw) e-jwT CS vi (jw) e-jwT
• CI
• Leads to frequency response
• v0 (jw) (1 e-jwT) CS vi (jw) e-jwT
• CI
• v0 (jw) - CS 1
• vi CI 1 ejwT
• ejw cos w j sin w

(
)
9
Behavior (continued)

• sin w 1 (ejw ejw)
• 2 j
• Define w0 f CS / CI
• Reduces to
• v0 (jw) 1 wT/2
  e-jwT/2
• vi jw / w0 sin wT/2
• f 1/T
• Becomes 1 if
  frequency ltlt f
• wT ltlt 1, so e-jwT/2 e0
  1

(
)
10
Behavior (concluded)

• wT/2 1
• sin wT/2
• Sampling capacitor switches equivalent to
  R 1 / (f CS)

11
OPAMP Performance Parameters
12
OPAMP Performance Parameters

• 5 V Power Supply 4 mm Silicon-Gate CMOS
  Technology

13
Resulting OPAMP Requirements

• O/P voltage must update to required accuracy (0.1
  ) with ½ clock period (1 ms for voice band
  filters)
• Important performance parameters
• Power dissipation
• Maximum capacitive load
• Open-loop voltage gain
• Output voltage swing
• Equivalent input flicker noise
• Equivalent input thermal noise
• Power supply noise rejection ratio (PSRR)
• Die area

14
Important Considerations for Non-Integrator
Applications

• Common-mode rejection ratio (CMRR)
• Common-mode range
• MOS inherently has a capacitive sample hold
  capability, so DC offsets can often be eliminated
  at sub-system level
• Makes OPAMP offsets less important

15
Two-Stage CMOS OPAMP
16
Bipolar OPAMP

• Uses single pole-splitting capacitor

17
nMOS Technology OPAMP
18
CMOS OPAMP
19
Voltage Gain Av

• Find by considering 2 stages separately
• Infinite CMOS input impedance means that there is
  no loading
• First-stage gain of CMOS OPAMP
• Av1 gm1
• g02 g04
• gm1 transconductance of input transistors
• g0 small-signal device output conductance
• Second-stage gain
• Av2 -gm6 (from earlier
  lecture)
• g06 g07
• Need Av 2000, so each stage needs gain 50

20
Voltage Gain (concluded)

• Choose transistor biases and W/L so that (VGS
  Vt) is 0.2 V
• Make drain depletion region lt 1/5 Leff with
  drain bias of several V.

21
Offsets

• DC offset has systematic offset and random offset
• Systematic from circuit design
• Random due to device mismatches
• Systematic offset
• Low gain per stage, so offsets in both stages
  important
• Ground both 1st stage inputs
• Voltages equal at drains of M3 M4
• vi2 voltage to force output V to 0 may differ
  from vo1

22
Circuit Example
23
Offsets (continued)

• Assume 1st stage gain of 50
• Each 50 mV difference between vi2 and vo1 results
  in 1 mV of input referred systematic offset
• Must choose W/L of M3, M4, M6 so that J equal
  in all 3 devices
• (W/L)3 (W/L)4 (1/2) (W/L)5
• (W/L)6 (W/L)6 (W/L)7
• Choose same L for M3, M4, M6
• Vary Ws to achieve same ratios
• Conflicts with low-noise requirementM3 and M4
  should have low gm
• Conflicts with frequency response requirement for
  capacitive loading M6 should have high gm

24
Random Input Offset

• More problematic with MOS than with bipolar
• VOS DVt (1-2) DVt (3-4) gm3
• gm1
• (VGS Vt) (1-2) DW/L(1-2)
  DW/L(3-4)
• 2 (W/L)
  (1-2) (W/L) (3-4)
• Minimize DVt (3-4) by making gm of loads small
  compared to gm of input transistors
• Minimize third term by making (VGS Vt) 50 to
  200 mV

(
)
25
OPAMP Design and Compensation

• Requirements
• Internal amplifiers load on amplifier is
  well-defined often purely capacitive (a few
  pFs)
• Output buffers Only a few amplifiers must drive
  an off-chip signal where capacitive and resistive
  loads are significant and variable

26
Frequency Response and Negative Feedback

• Compensate with a pole-splitting capacitor
• Negative feedback can cause oscillation
  eliminate with compensation circuit
• Negative feedback reduces gain by (1 T) factor
• T loop gain

27
Negative Feedback Benefits

• Stabilizes amplifier gain against active device
  parameter changes due to
• VDD variation
• Temperature changes
• Device aging
• Lets designer modify input/output impedances
• Reduces signal waveform distortion
• High-quality audio amplifiers use it around power
  output stage
• Can increase circuit bandwidth widely used in
  broadband amps

28
Negative Feedback Disadvantages

• Reduces gain in proportion to above benefits
• Requires more amplifier stages
• Feedback can cause oscillation
• Must design to avoid that

29
Ideal Feedback

• so a se
• sfb f so
• se si sfb si f so
• so a si a f so
• so A a
  (8.5)
• si 1 a f
• A closed loop gain

30
Ideal Feedback (continued)

• T loop gain
• T a f
• so A a
• si 1 T
• When T gtgt 1, A 1 / f
• So feedback transfer function determines
  amplifier gain
• Feedback loop forces sfb to nearly equal si
• Amplifies se si sfb , effectively
  minimizes se

31
Ideal Feedback (concluded)

• se si f a si
• 1 a f
• se 1 1 when T gtgt
  1, se ltlt si
• si 1 a f 1 T
• sfb f si a
• 1 a f
• sfb T when T gtgt 1, then sfb
  si
• si 1 T

32
Feedback Comments

• If f lt 1, then so is an amplified replica of si
• Usually, gain a of the amp. is ill-defined,
  depends on
• Temperature
• Active transistor operating conditions
• Transistor parameters (b, etc.)

33
Gain Sensitivity

• Differentiate Eqn. (8.5)
• dA (1 a f) a f 1
• da (1 a f)2 (1 a f)2
• If a changes by d a, then A changes by d A
• dA d a
• (1 a f)2
• dA 1 a f d a d a / a
  d a / a
• A a (1 a f)2 1 a f
  1 T

34
Low-Frequency Gain

• Fractional change in A is reduced by (1 T)
  compared to fractional change in a
• If T 100 and a changes by 10 (Temp.), then A
  only changes by 0.1
• Effect of negative feedback on distortion
• Negative feedback is effective in reducing
  distortion
• Distortion is due to changes in slope of
  basic-amplifier transfer characteristic
• Feedback reduces effect of slope changes
• A is relatively independent of a

35
Basic Amplifier Transfer Characteristic
36
System Transfer Function with Feedback
37
Modified Transfer Characteristic for Distortion

• Use feedback with amplifier characteristic, but
  overall gain still given by Eqn. (8.5)
• Must use a1 or a2, depending on region in
  transfer characteristic
• Overall system transfer characteristic also has 2
  regions of different slopes
• Slopes A1 A2 are almost equal due to negative
  feedback
• A1 a1 1
• 1 a1 f f
• A2 a2 1
• 1 a2 f f

38
Negative Feedback Conclusions

• The feedback amplifier has much less
  non-linearity than the basic amplifier
• Horizontal scale in system transfer function is
  compressed compared with amplifier transfer
  function
• Negative feedback reduces gain by (1 T)
• Causes few serious problems just place a
  preamplifier in front of the feedback amplifier
• Preamp handles much smaller signals than the
  amplifier, so distortion is not a problem in the
  preamp

39
System Transfer Function

• Hard saturation of output amplifier at output
  level So2
• Output becomes independent of input
• Slope a3 0 in that region, so negative feedback
  cannot help there

40
Gain Magnitude vs. Frequency
41
Analysis for Bode Plot

• vo a (s) ve
• ve vi - f vo
• vo a (s) (vi f vo)
• vo (1 a (s) f) a (s) vi
• A (s) vo a (s)
  (9.2)
• vi 1 a (s) f
• Has a single pole
• a (s) a0
  (9.1)
• 1 s / p1
• a0 low-frequency gain

42
Amplifier Gain

• a0 low-frequency gain
• p1 basic amplifier pole (radians/sec)
• Assume a resistive feedback path so f is constant
• Loop gain T (s) a (s) f
• Substitute (9.1) into (9.2)

43
Low Frequency Gain

• Look at -3 dB bandwidth of the feedback circuit
  (new pole frequency)
• Feedback reduced low frequency gain by (1 T0) ,
  but increased the -3 dB frequency by (1 T0)
• Therefore, gain-bandwidth product is constant

44
Usage

• Negative feedback widely used for designing
  broadband amplifiers
• Make up for loss of gain with additional amp.
  stages
• Consider effect of feedback on pole of A (s)
  overall transfer function

45
Locus of Pole Root-Locus Diagram

• As T0 increases, magnitude of pole of A (s)
  increases
• Pole moves out on negative real axis as T0
  increases

46
Instability and Nyquist Criterion

• Above example assumed that amp. had a single
  pole transfer function
• Closely approximated by internally compensated
  OPAMPS like the 741
• Many other amps. have multi-pole transfer
  functions
• Results deviate
• Compensation Design process to overcome problems
  of poles in transfer function

47
Example Amplifier with 3 Pole Transfer Function
48
Poles in s Plane
49
Plot of Gain Magnitude and Phase vs. f

• Assume factor of 10 separation between poles

50
Comments

• Above p1, plot of a (jw) falls at 6 dB/octave
• ph a (jw) approaches -90o
• Above p2, get 12 dB/octave and -180o
• Above p3, get 18 dB/octave and -270o
• w180 frequency where ph a (jw) -180o
• a180 value of a (jw) at this frequency
• Assume 3 widely separated poles then phase
  shifts at p1, p2, p3 are -45o, -135o, -225o

51
Negative Feedback

• Keep f constant, so loop gain T (jw) a (jw) f
  has same variation with w as a (jw)
• Plot of a f (jw) T (jw) in magnitude and phase
  on a polar plot vs. w is the Nyquist Diagram

52
Nyquist Diagram
53
Nyquist Diagram Comments

• Variable on the curve
• For w 0, T (jw) T0 and ph T (jw) 0
• Curve meets the real axis with intercept T0
• As w increases, a (jw) decreases ph a (jw)
  becomes negative plot is in quadrant IV
• As w ?8, ph a (jw)? -270o and a (jw)?0
• Plot asymptotic to origin and tangent to the
  imaginary axis
• At w180, phase is -180o and curve crosses
  negative real axis
• If a (jw180) f gt 1, then at this point the
  Nyquist Diagram will encircle the point (-1, 0)

54
Nyquist Criterion for Amplifier Stability

• If the Nyquist plot encircles the point (-1, 0)
  the amplifier is unstable
• Equivalent to a mathematical test for poles in
  the right half plane
• Poles in right half plane make the circuit
  oscillate
• of encirclements of (-1, 0) gives the of
  right half plane poles
• Here there are 2

55
Poles in the Right Half Plane

• Complex poles
• Then, transient response has a term
• (A growing sinusoid if s1 is positive)
• Term is present even if no further input applied
• Makes circuit unstable or oscillatory
• Now, let Nyquist diagram pass through (-1, 0)
• Then, at w180 T (jw) a (jw) f -1 and A
  (jw) 8
• Feedback amp. has a forward gain of 8
• Onset of instability and oscillation
• This is where poles of A (s) are on the jw axis
  in s plane

56
Nyquist Diagram

• Then, increase T0 by increasing a0 or f, and the
  Nyquist Diagram expands linearly and it encircles
  (-1, 0)

57
Simpler Test

• If T (jw) gt 1 at the frequency ph T (jw)
  -180o, then the amplifier is unstable

58
3-Pole Amplifier Gain and Phase
59
Comments

• Also plotted 20 log 10 1/f, which approximates
  the low frequency gain in decibels with feedback
  applied since
• Consider vertical distance x between 20 log 10 a
  (jw) and 20 log10 1/f
• x is a direct measure in decibels of T (jw),
  loop gain magnitude

60
Observations

• Point where curve of 20 log10a (jw) intersects
  line 20 log10 1/f is the place where the
  loop-gain magnitude T (jw) is 0 dB or unity
• Curve of a (jw) in decibels can be the curve of
  T (jw) in decibels if the dotted line at 20 log
  1/f is taken as a zero axis
• Gain curve vs. f with feedback applied follows 20
  log10 A0 line until it intersects the gain curve
  20 log10 a (jw)
• At higher frequencies, 20 log10 A (jw) just
  follows curve of 20 log10a (jw) for the
  basic amplifier

61
More Observations

• So, at higher f, T (jw)?0 and the feedback has
  no influence on amplifier gain
• Loop-gain magnitude T (jw) is 1 at frequency w0
• Here, the phase has not reached -180o at w0
• Using modified Nyquist criterion, then the
  feedback loop is stable
• Clearly T (jw) lt 1 at frequency where ph T (jw)
  -180o
• You would find from the polar Nyquist Diagram
  that it does not encircle (-1, 0)

62
Phase Margin

• As T (jw) is made closer to 1 at the frequency
  where ph T (jw) -180o the amplifier has a
  smaller margin of stability
• Specify in 2 ways
• Phase margin 180o (ph T (jw)) at frequency
  where T (jw) 1
• Gain margin T (jw) in dB at the frequency
  where ph T (jw) -180o
• Must be lt 0 for stability

63
Significance of Phase Margin

• Feedback amp., single pole response
• Phase margin is 90o if low-frequency loop gain is
  fairly large
• Typical lower allowable limit is 45o, with 60o as
  a more common value

64
Phase Margin
65
Feedback Amp. with 45o Phase Margin

• Real and constant feedback function f
• So, ph T (jw0) 135o
  (9.11)
• w0 is frequency where
• Substituting (9.11) and (9.12) into (9.14)

66
Interpretation

• w0 where T (jw0)1 is the nominal -3 dB point
  for a single pole basic amplifier
• Here there is 2.4 dB (1.3 X) of peaking above the
  low-frequency gain of 1/f
• Consider a phase margin of 60o
• Then, at w0 ph T (jw0) -120o, T (jw0) 1
• A similar analysis gives A (jw0) 1/f
• No peaking at w w0, but no gain reduction,
  either

67
Phase Margin of 90o

• Then, at w0 ph T (jw0) -90o, T (jw0) 1
• A (jw0) 0.7 / f
• Here the gain at w0 is 3 dB below the midband
  value
• Plot gain vs. f for various phase margins
• Plots assume that the response is dominated by
  the 1st 2 poles of the transfer function
• Note 90o phase margin has only 1 pole
• As phase margin?0, gain peak increases and
  approaches 8 and oscillation occurs

68
Gain vs. Normalized Frequency for Various Phase
Margins
69
Gain Peak

• Usually at f where T (jw) 1, but for 60o
  phase margin, have 0.2 dB peaking just below w0
• After peak, curves approach an asymptote
  of -12 dB/octave for phase margins other
  than 90o
• Due to open-loop gain falling at -12 dB/octave
  due to 2 poles in the transfer function

70
Compensation Theory
71
Compensation Theory

• Revisit amplifier
• Forward gain was A0, positive phase margin
• Stable
• If feedback increased by making f larger (A0
  smaller), oscillation eventually happens

72
Gain Phase vs. Frequency
73
Compensation

• f1 chosen to give 0 phase margin
• Corresponding overall gain is A1 1/f1
• If feedback increased to f2, so A2 1/f2, phase
  margin is negative and circuit oscillates
• Conclusion If amp. to be used in feedback loop
  with loop gain gt a0 f1, must increase phase
  margin
• Called compensation
• Without it, forward gain cannot be made less
  than A1 1/f1 due to oscillation

74
Most Common Method

• To compensate, reduce amp. bandwidth
  (narrowbanding)
• Deliberately introduce a dominant pole
• Forces phase shift to be lt 180o when loop gain
  1
• Directly sacrifice frequency capability of amp.
• Hardest case to compensate f 1 (unity gain
  feedback)
• Introduce new dominant pole at pD

75
Compensation Changes Bode Plot
76
Analysis

• Assume that pD does not affect original amp.
  Poles at p1, p2, and p3
• Often not true, but true of 702 OPAMP
• New dominant pole at pD causes gain to
  decrease at 6 dB/octave until frequency p1 is
  reached
• In this region, amp. phase shift asymptotes to
  -90o
• If pD chosen so that gain a (jw) 1 at
  frequency p1, then loop gain is also 1 at p1
  for unity feedback f 1
• Phase margin here is 45o, so amp. is stable
• Original amp. would have been unstable here

77
Cost of Stability

• With feedback removed, amp. has unity-gain
  bandwidth of only p1, much less than before
• With feedback applied, loop gain starts
  decreasing at pD, and feedback benefits
  diminish as loop gain decreases
• Shunt feedback at I/P or O/P of amp. reduces
  basic terminal impedance by 1T (jw)
• T (jw) depends on frequency, so terminal Z of
  shunt-feedback amp. begins to rise when T (jw)
  starts to decrease
• High-frequency terminal Z will appear to be
  inductive

78
Example

• Calculate dominant pole frequency required to
  give unity-gain compensation of the 702 OPAMP
  with phase margin of 45o
• Low-frequency gain a0 3600
• Poles
• p2 is so close to p1 that there is significant
  phase shift at -3 dB frequency
• Approach
• Use above approximate results
• Estimate required dominant pole frequency
• Empirically adjust frequency to obtain required
  results

79
Analysis

• Introduce dominant pole pD so that a0 3600
  becomes 1 at p1/2p 1 MHz with a 6 dB/octave
  decrease as a function of frequency
• 6 dB/octave indicates direct proportionality
  gives
• Gives transfer function of
• Pole frequencies in radians/sec.

80
Analysis

• Gives unity gain frequency (a (jw) 1) of 780
  kHz
• Lies below design value of 1 MHz because actual
  gain curve is 3 dB below asymptote at break
  frequency of p1
• Also, at 780 kHz, phase shift from Eqn. 9.21 is
  -139o instead of desired -135o (including
  contribution of -11o from p2)
• Close enough for government work!

81
Exact Phase Margin

• Can achieve exact phase margin of 45o by
  empirically reducing pD until Eqn. 9.21 gives
  phase shift of -135o at unity gain frequency
• Happens when
• Gives unity gain frequency at 730 kHz
• Consider amp. performance (dominant pole at pD
  ) when used in feedback loop with f lt1 (a0 gt1)

82
Bode Plot
83
Comments

• Loop gain falls to 1 at frequency wx and phase
  margin is 90o
• -3 dB bandwidth of feedback circuit is wx
• Circuit has too much compensation bandwidth is
  wasted
• OPAMPs are general purpose circuits, with various
  feedback circuits with 0 f 1
• Optimum bandwidth achieved if user adds
  compensation
• User tailors compensation to required gain value
• Gives much higher bandwidth for high-gain
  circuits

84
Compensation

• Compensation of amplifier characteristic for
  operation in feedback circuit with forward gain
  A0
• Dominant pole added at pD to give 45o phase
  margin
• pD gtgt pD

85
Bode Plot
86
Compensation

• -3 dB bandwidth of amp. is p1, loop gain is 0
  dB
• -3 dB frequency would only be wx p1 / A0 if
  unity-gain compensation used
• Assumption Original amplifier poles were
  unaffected by addition of dominant pole
• For bandwidth, more efficient to compensate by
  adding capacitance so that original amp. dominant
  pole p1 is reduced so that p1 performs
  compensation
• Need
• Access to internal nodes
• Knowledge of where to add C to reduce p1

87
Compensation
88
Compensation

• Assume that p2 and p3 unaffected by procedure
• Compensation by reducing p1
• Dominant pole magnitude p1 must cause gain to
  fall to 1 at p2
• Nominal bandwidth in unity-gain configuration is
  p2, and loop gain 1 at p2
• Better for preserving bandwidth than adding pD
• In practice, p2 is often 5 to 10 X p1, so
  bandwidth greatly improves

89
Use Minimal of Amplifier Stages

• Each stage adds more poles to transfer function
• Makes compensation harder, especially when wide
  bandwidth needed

90
Compensation Methods

• Add C to create dominant pole with desired
  magnitude

91
Compensation Methods

• Add large C between collectors of input stage in
  2-stage amp.
• Output broadband stage not shown

92
Compensation Methods

• C is doubled for the half-circuit
• If RS not large, major contributions to dominant
  pole from input C of Q4 and Miller Capacitance of
  Q4

93
Miller Capacitance

• Same model serves for both bipolar and MOS OPAMP

94
Half Circuit Models
95
Miller Capacitance

• Model has ro deleted (assumed to be much larger
  than RL)

96
Miller Approximation

• Look at input impedance across plane AA
• Current produced by voltage v1
• Output KCL

Miller Effect Admittance seen across plate
97
Miller Approximation

• Miller Effect complicated due to s dependence of
  Av (s)
• Replace Av (s) with low-frequency value Av (0)
• Miller Approximation is the use of low-f voltage
  gain
• CM Miller Capacitance
• From Eqn. (7.3), Av (0) -gmRL

98
Miller Approximation Circuit

• Use to form new equivalent circuit useful for
  calculating
• Forward transmission circuit
• Circuit input impedance
• Not useful for high-f reverse transmission or
  output Z
• Physical origin in Av of circuit
• At low f, small v1 produces large

99
Circuit with Miller Approximation

• v0

RL
100
Capacitance Transformation

• Voltage across CM only v1, but CM larger than Cf
  by (1 gm RL)
• Therefore CM conducts same current as Cf (assume
  that most of current goes across CM and not Cin
  or rin or RS)
• In figure, CM adds directly to Cin and therefore
  reduces amplifier bandwidth

101
Voltage Gain

• Leads to

102
Voltage Gain

• Single-pole circuit
• For s jw, Av is 3dB below low-f value at
• As Ct, RL, or RS increase, -3 dB f is reduced

103
Exact Analysis

• Analyze this circuit

104
Analysis

• Use Norton equivalent at input

105
Analysis
106
Analysis

• Differences from transfer function computed with
  Miller approximation
• vo/vi has a positive real zero with magnitude
  gm/Cf
• Zero stems from transmission of signal directly
  through Cf to O/P
• Effect small except at very high f neglect (But
  may be important for stability analysis)
• Write denominator of Eqn. (7.19) as

107
Analysis

• Transfer function has 2 poles real and widely
  separated

108
Analysis

• Substitute in value for R
• Almost exactly same as for Miller approximation,
  except for RL/R denominator term (usually small
  compared with (1gmRL)
• Miller calculation nearly equivalent to
  calculating dominant pole of amp. neglecting
  higher f poles
• Gives good estimate of w-3dB

109
Second Pole

• Get 2nd, non-dominant pole, by equating s2
  coefficients of Eqns. (7.19) (7.23)
• Use table to apply this analysis to bipolar
  (common-emitter) or MOS (common source) amp.
  circuits

110
Model Adjustment for Bipolar/MOS
111
Compensation Approach

• Reduce magnitude of dominant pole
• Compensation C changes higher f poles
• Use Spice to determine original pole positions
• Get 1st estimate of C, assuming no changes in
  higher f poles
• Check assumption with another simulation with C
  included
• Iterate until design satisfactory

112
Circuit for Analysis
113
Estimating Dominant Pole Magnitude

• Use zero-value time constant analysis
• If needed C very large, estimate dominant pole
  using only C
• Typically, get C gt 1000 pF as requirement
• Disadvantage Cannot realize large C on chip
• For internally compensated OPAMP, must use C lt 50
  pF
• Solution Use Miller Multiplication of the C

114
Simplified 741 OPAMP
115
Compensation

• Connect 30 pF C around Darlington pair Q16 Q17
• Produces a pole with p 4.9 Hz
• Changes gain phase of 741 OPAMP as shown

116
741 Compensation Results
117
Compensation Results

• Unity gain fT 1.25 MHz
• Phase Margin 80o
• Low f gain 108 dB
• Compensation has another advantage
• Pole-splitting

118
Before Compensation
119
Poles and Zeroes of 741 After Compensation
120
Before Compensation

• Before compensation
• 2 important low f poles pD 18.9 kHz, p2
  328 kHz
• pD due to shunt C at base of Q16
• p2 contributed by Q16 Q17
• Rest of poles zeroes come from I/P O/P stages
  other parts

121
After Compensation

• Dramatic change in poles zeroes
• New pD 5 Hz
• Original 2nd-most dominant pole removed
• 2nd higher most dominant poles form cluster,
  real magnitudes 10 to 15 MHz, including complex
  poles
• Amp. gain must fall to 1 at f below 2nd-most
  dominant pole (for adequate phase margin)
• Removal of pole at 328 kHz has greatly increased
  realizable bandwidth
• Without pole movement, compensation C would have
  to be set to make gain of 741 fall to 1 at f lt
  328 kHz

122
Replace Darlington Pair with Single Transistor
Fed by Prior Stage Current

• R1 (R2) total shunt resistances at I/P (O/P)
• Includes transistor input O/P resistances
• C1 (C2) total shunt C at I/P (O/P)
• C is transistor Cbc compensation C

123
Analysis

• Has positive real zero z gm / C
• Usually so large that it can be neglected in
  bipolar ckts.
• May have to be considered in MOS, because of low
  gm
• Two-pole transfer function
• If the poles are real widely separated (usually
  true).

124
Poles

• since the Miller effect from C will dominate for
  large C and gmR1, gmR2 gtgt 1
• Dominant-pole magnitude p1 decreases as C
  increases, but p2 increases as C increases

125
Pole Movement
126
Limits

• As C becomes gtgt C1 or C2
• This circuit has only 2 poles
• Assume a large C, then Eqn. (9.32) gives p1
• Estimate p2 from time constants of other
  capacitors with C shorted, C1 ? C2 connected in
  parallel with C shorted
• Also, v1 controlling dependent current
  source appears across that source (behaves like a
  resistance of value 1 / gm)
• 1 / gm now parallel with R2

127
Limits (contd.)

• Poles at C 0 are

128
Conclusion

• Original ckt. has 2 poles
• Compensation C provides feedback
• Makes 2nd stage behave as an integrator
• Poles split apart as C increases
• One goes to low f (DC) and the other towards
  high f (-8)
• Approximates real integrator, which has only 1
  pole at DC

129
Poorer Approach

• Add shunt C from base of Q16 to ground

130
Poorer Approach

• To achieve phase margin of 80o, need 0.3 mF
  compensation C
• Gives p1 dominant at 0.27 Hz
• fT (unity gain) at 63 kHz, p2 294 kHz
• Very little movement of 2nd-most dominant pole
  occurred, decreased pole magnitude
• Consequence Realizable bandwidth of compensated
  circuit is 1/20 of that obtained using Miller
  Multiplication
• Also, cannot realize a 0.3 mF C on chip
• Cgd of MOSFET leads to pole splitting because of
  Miller effect

131
Two-Stage MOS Amp. Compensation
132
Two-Stage MOS Amp. Compensation

• Poles/zero
• But MOSFT gm is 10 X lower than bipolar gm
• So, right half-plane zero may be below nominal fT
  of amp.

133
Compensation
134
Problems with p2

• At z, gain characteristic flattens zero
  contributes 6 dB/octave
• At z, phase becomes 90o more negative due to
  zero
• Consequence Amp. has negative phase margin is
  unstable when influence of next most dominant
  pole p2 is felt
• Zero halts the gain roll-off needed for stability
  pushes phase in negative direction
• Low MOSFET gm reduces p2 relative to bipolar one

135
Phase Shift Problems

• At high f, feedforward through C overwhelms
  normal gain path via gm of 2nd stage
• Feedforward path does not have normal 180o phase
  shift of normal gain stage gain path loses an
  inverting stage
• So, any feedback applied around amp. is positive,
  not negative oscillates
• At very high f, C is a short circuit diode
  connecting 2nd stage (with resistive load 1 / gm)
  to 1st stage again lose 180o phase shift

136
Right Half-Plane Zero

• Due to interaction of gm current and
  frequency-dependent current through C
• Current gmv1 flows out of O/P node
• Total O/P node current related to v1
• Zero exists where this current is 0 (z gm / C)

137
3 Ways to Eliminate Effect of Zero

• Put source follower in series with compensation C

138
3 Ways to Eliminate Effect of Zero

• Put source follower in series with compensation C
• Blocks feedforward current through C from
  reaching O/P eliminates zero Use model of fig
  9.24 (b), (9.25) still holds
• Same elements at I/P node, voltage across C still
  (vo-v1)
• New equation for summing currents at O/P (no
  current through C to O/P due to buffer)

139
Analysis

• Combine with (9.25) to get
• No more zero! If gmR1, gmR2 gtgt 1 and large C
• Dominant pole p1 did not change, and p2 is almost
  as before if C2 gtgt C1
• Drawback Got rid of zero, but follower has extra
  devices extra bias current and non-zero DC
  voltage between I/P and O/P affects voltage
  swing since source-follower must remain in active
  region to maintain feedback through C

140
Second Approach

• Block feedforward current through C with
  common-gate transistor

141
Second Approach

• M11 lets current flow from O/P back towards I/P
  of 2nd stage
• But, large impedance looking into drain of M11
• So, feedforward current through C is small
• When it is 0, eliminate right half-plane zero

142
2nd Approach (contd.)

• Simplified small-signal model for common-gate
  stage C
• M11 is ideal current buffer. Plug into figure
  get
• Combine to get
• No more zero!

143
Pole Locations

• Assume gmR1, gmR2 gtgt1, get
• p1 same as before, but p2 changed to higher f
• Because C gtgt C1, when C C2, so C2 gtgt C1
• Allows use of a smaller compensation C
• Advantage Better high f negative power supply
  rejection than Miller compensation

144
Miller Compensation

• C connected from gate to drain of M6 (nFET in 2nd
  stage)
• Shorts gate drain at high f
• If Vgs6 roughly constant, high f variations in
  negative supply couple directly to OPAMP O/P
• Drawbacks of common-source stage
• Extra devices more DC current needed
• Also, if 2 I2 current sources are mismatched,
  differential current flows in I/P stage
• Unbalances I/P stage and aggravates OPAMP I/P
  offset Volt.

145
1st Stage with Cascode Transistor
146
1st Stage with Cascode Transistor

• Reduces feedforward current through C, compared
  to a C connection at node Y
• If voltage swing at source of cascode device lt
  swing at drain
• Eliminates feedforward path, and therefore zero,
  if voltage swing a cascode device source is 0
• Advantage Avoids extra devices, bias current,
  mismatch problems

147
Third Approach

• Insert R in series with C
• R modifies but does not eliminate feedforward
  current
• Moves zero to 8
• So total forward current at O/P due to v1?0 as
  w?8
• At w?8, C is a short circuit so feedfoward
  current is

148
Third Approach

• At w?8, C is a short circuit so feedfoward
  current is
• Add to current from gm source

149
Third Approach

• When w ?8 if RZ 1 / gm, term vanishes and zero
  is at 8
• Carry out prior analysis

150
Analysis

• Assume gmR1, gmR2 gtgt 1 and large C
• p1 and p2 same as in original circuit. p3 is at
  very high f
• 3 poles due to 3 independent Cs
• Prior method had 3 Cs forming a loop, so only 2
  C voltages are independent

151
Zero

• Moves to 8 when RZ 1 / gm
• Making RZ gt 1 / gm moves zero into left
  half-plane
• Provides positive phase shift at high f and
  improves phase margin of feedback circuit using
  OPAMP

152
Compensated Circuit
153
Small-Signal Model
154
Transistor to Implement RZ

• Behaves like R if
• Make R of triode transistor track 1 / gm of M6 if
  two transistors are identical and have same VGS
  Vt
• R transistor source voltage set by VGS6, which is
  nearly constant
• Set VGS of triode by connecting gate to a DC bias
  Volt.

155
Summary of Series C and R Compensation

• Dominant pole set by C, independently of C2
  (load capacitance)
• Second pole is function (C2)
• Must select C to give acceptable phase margin for
  largest C2
• Phase margin increases as C2 decreases p2 a 1
  / C2

156
Summary

• Switched-Capacitor Filter Using OPAMP
• OPAMP Performance Parameters
• Negative Feedback
• OPAMP design and compensation
• Miller Approximation