Standard Cell Characterization Considering Lithography Induced Variations Enable Lithoaware Static T PowerPoint PPT Presentation

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Title: Standard Cell Characterization Considering Lithography Induced Variations Enable Lithoaware Static T


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Standard Cell Characterization Considering
Lithography Induced Variations - Enable
Litho-aware Static Timing Analysis
  • Ke Cao()(), Sorin Dobre(), Jiang Hu()
  • Dept of Electrical Engineering, Texas AM
    University
  • Qualcomm, Inc.

2
Acknowledgements
  • We would like to thank the following people for
    their contribution for this work.
  • Foua Vang standard cell library support.
  • Kasim Mahmood Hspice model support.
  • Dan Perry CAD support.
  • Riko Radojcic technical suggestions and
    discussion.
  • Matt Nowak management support.
  • Bill Graupp tool support.

3
Outline
  • Motivation.
  • Methodology details.
  • Current approaches.
  • Test pattern.
  • Dummy poly insertion.
  • Modeling poly gate shapes.
  • Proposed flow.
  • Experimental results.
  • Conclusion and future work.

4
Motivation
  • Shape deviation due to Litho effects are not
    negligible.
  • Litho effects are systematic.
  • Current process corner methodology is pessimistic.

Shape contours generated by Mentor Graphics
LFD.
5
Current Approach
  • Issues
  • It is intrusive to the current flow.
  • Litho simulation is expensive on block/chip
    level.
  • Standard cell needs to be characterized for
    almost every instantiation.
  • Design optimization is not straightforward.
  • It is not clear how this flow can be scaled to
    SSTA.

6
Reasonable assumptions
  • Interconnect timing variation.
  • Still dominated by thickness variation due to CMP
    in 65nm.
  • May not be true going forward.
  • Litho-induced standard cell timing variation is
    poly gate-length dominated.
  • Gate width and diffusion variations impacts on
    timing are small.
  • Can be easily considered in our litho flow.
  • Litho interaction for poly gate length in a row
    based standard cell block comes from the
    neighboring cells in the same row.
  • Space for poly gates are large for gates in
    different rows.
  • Poly routing on top and bottom of the cells are
    being phased out.
  • Poly extension over diffusion provides enough
    space for a reasonably good OPC algorithm to
    recover.

7
Litho variation test structures
  • Typical Litho interaction range is 0.6um-1um in
    65nm node.
  • The closest neighboring shapes have the most
    influences.
  • Shapes with the fixed closest neighbors are not
    sensitive to proximity topology.

8
Dummy poly insertion in standard cells
  • Impact
  • Providing the fixed closest neighbor for poly
    gate at boundary.
  • Fixed litho aware timing model for standard
    cells.
  • Cost
  • Restriction field poly for cells should not be
    at cell boundary.
  • No other DRC violation.
  • No LVS error dummy poly is not a device.
  • No area penalty.
  • Gap between diffusions of different cells is
    usually greater than minimum.
  • Cells have to be on grid, which provides
    additional white space.

9
Shape analysis
  • Calculate Ids for Ion and Ioff.
  • Match Ion and Ioff in lookup table with same W to
    get Leff for timing and leakage.
  • Back annotate Leff_timing

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Litho-aware standard cell characterization
Lookup table for Ion and Ioff
Calculate Ids for Ion and Ioff
Generate effective L for timing and leakage
Litho Simulation
Cell Characterization
Back annotate into cell netlist
.lib and .db for standard cell lib
  • Look up table can be generated separately.
  • Two netlists are generated for each standard
    cell,one for timing characterization and one for
    leakage characterization.

11
Proposed flow
  • Advantage
  • Design flow does not change. Litho simulations
    are not visible to designers. No issue with
    design optimization.
  • Litho simulation happens off-line, in standard
    cell characterization phase. Each cell is
    characterized ONCE.
  • Can afford to run litho simulation on standard
    cells in the most accurate mode.
  • Portable to SSTA flow.

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Experimentstandard cell timing and leakage
variability
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Experiment Block level timing variability
  • 400 most timing critical paths in 65nm 250MHz
    block.
  • Variability of paths timing decreased by an
    averageof 320ps.

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Conclusion
  • Simulation data shows litho-aware timing analysis
    helps to peel out the litho-induced systematic
    timing variations from the corner models to
    reduce timing uncertainty.
  • The litho-aware timing analysis flow does not
    have to impact the traditional flow, even though
    litho effects are proximity dependent.
  • The scheduling impact of enabling the litho-aware
    timing analysis is minimal even if we use the
    most sophisticated litho simulation tool for most
    accurate results.
  • Future works include interconnect litho
    variation timing impact, litho aware SSTA.

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Thank you!
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