SYNTHESIS AND OPTIMIZATION OF VLSI CIRCUITS R Vinod

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SYNTHESIS AND OPTIMIZATION OF VLSI CIRCUITSR
Vinod
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MICROELECTRONICS

• INFORMATION SYSTEMS
• TELECOMMUNICATIONS
• CONSUMER PRODUCTS
• ROBOTICS
• SIGNAL PROCESSING

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• SMALLER CIRCUITS(AREA)
• LOWER POWER CONSUMPTION
• HIGHER PERFORMANCE
• HIGHER RELIABILITY
• LOWER COST

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MODELLING

• STRUCTURAL
• BEHAVIOURAL
• DATAFLOW

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• SYNTHESIS OF VLSI CIRCUITS

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SYNTHESIS

• WHAT IS SYNTHESIS?
• TRANSFORM BEHAVIOURAL INTO STRUCTURAL VIEW!!

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ARCHITECTURE LEVEL SYNTHESIS

• ARCITECTURAL LEVEL ABSTRACTION
• DETERMINE MACROSCOPIC STRUCTURE
• EXAMPLE MAJOR BUILDING BLOCKS

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MOTIVATION FOR SYNTHESIS

• REDUCE SPECIFICATION OF DETAILS
• EXTEND DESIGNER BASE
• SELF DOCUMENTING DESIGN SPECIFICATIONS

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MOTIVATION FOR SYNTHESIS

• REDUCE DESIGN TIME
• EXPLORE AND OPTIMIZE MACROSCOPIC STRUCTURES
• --SERIES / PARALLEL EXECUTION OF
• OPERATIONS

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HARDWARE COMPILATION

• COMPILE HDL MODEL INTO SEQUENCING GRAPH
• OPTIMIZE SEQUENCING GRAPH
• GENERATE GATE LEVEL INTERCONNECTION FOR A CELL
  LIBRARY

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ARCHITECTURAL SYNTHESIS AND OPTIMIZATION

• SYNTHESIZE MACROSCOPIC STRUCTURE INTO BILDING
  BLOCKS
• MAXIMIZE PERFORMANCE IMPLEMENTATIONS SUBJECT TO
  AREA CONSTRAINTS

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ARCHITECTURAL SYNTHESIS AND OPTIMIZATION

• MINIMUM AREA IMPLEMENTATIONS SUBJECT TO
  PERFORMANCE CONSTRAINTS
• DETERMINE AN OPTIMAL IMPLEMENTATION
• CREATE MODEL FOR DATAPATH AND CONTROL

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STANDARD RESOURCES

• EXISTING MACRO CELLS
• EXAMPLE ADDERS AND MULTIPLIERS
• APPLICATION SPECIFIC RESOURCES
• EXAMPLE INSTRUCTION DECODER
• (YET TO BE SYNTHESIZED)

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CIRCUIT FAMILIES

• RESOURCE DOMINATED CIRCUITS
• AREA AND PERFORMANCE DEPEND ON FEW WELL
  CHARCTERISED BLOCKS
• EXAMPLE DSP CIRCUITS

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CIRCUIT FAMILIES

• NON - RESOURCE DOMINATED CIRCUITS
• AREA AND PERFORMANCE ARE LARGELY INFLUENCED BY
  SPARSE LOGIC ,CONTROL AND WIRING
• EXAMPLE SOME ASIC CIRCUITS

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SYNTHESIS IN THE SPATIAL DOMAIN

• BINDING
• ASSOCIATE A RESOURCE WITH EACH OPERATION WITH THE
  SAME TYPE
• SHARING
• BIND A RESOURCE TO MORE THAN ONE OPERATION

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SYNTHESIS IN THE TEMPORAL DOMAIN

• SCHEDULING
• ASSOCIATE A START TIME WITH EACH OPERATION
• DETERMINE LATENCY AND PARALLELISM OF THE
  IMPLEMENTATION

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ESTIMATION

• RESORCE DOMINATED CIRCUITS
• AREA SUM OF THE AREA OF THE RESOURCES BOUND TO
  THE OPERATIONS
• DETERMINED BY BINDING
• LATENCY START TIME OF THE SINK OPERATION
  START TIME OF THE SOURCE OPERATION
• DETERMINED BY SCHEDULING

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ESTIMATION

• NON RESOURCE DOMINATED CIRCUITS
• AREA ALSO AFFECTED BY REGISTERS, STEERING LOGIC
  , WIRING
• CYCLE TIME ALSO AFFECTED BY REGISTERS, STEERING
  LOGIC , WIRING

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SCHEDULING

• SEQUENCING GRAPH
• CYCLE TIME IS GIVEN
• DETERMINE THE START OF THE OPERATION
• GOAL DETERMINE AREA / LATENCY TRADE-OFF

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FIELD PROGRAMMABLE GATE ARRAYS (FPGAs)

• A POPULAR TECHNOLOGY FOR SYNTHESIS
• PROGRAMMABLE BY THE USER
• ARRAYS OF LOGIC GATES USED AS BUILDING BLOCKS TO
  BUILD THE COMPLETE CIRCUITRY

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WHERE IS IT USED?

• SYNTHESIS OF THE DESIGN OF CONSUMER PRODUCTS LIKE
  CELL PHONES
• SYNTHESIS PLAYS A MAJOR ROLE IN INTERCHANGING
  TECHNOLOGY

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SYNTHESIS OF PIPELINED CIRCUITS

• PIPELINED CIRCUITS
• CONCURRENT EXECUTION OF OPERATIONS ON DIFFERENT
  DATA SETS
• PRESERVE LATENCY
• INCREASE THE THROUGHPUT RATE
• INCREASE THE I / O RATE

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SYNTHESIS OF PIPELINED CIRCUITS

• APPLICABLE TO
• GENERAL PURPOSE PROCESSORS
• DSPS
• SCHEDULING FOR PIPELINED CIRCUITS
• CYCLE TIME
• DELTA DELAY
• KEY FACT SIMULTANEOUS OPERATIONS AT STEPS
• REDUCED SHARING

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ALGORITHMS FOR SCHEDULING

• HEURISTIC ALGORITHMS
• SET OF THUMB RULES FRAMED BY THE USER TO INCREASE
  EFFICIENCY
• LOOP FOLDING
• REDUCE EXECUTION DELAY OF A LOOP

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DATA PATH SYNTHESIS

• CONNECTIVITY SYNTHESIS
• CONNECTION OF RESOURCES TO MULTIPLEXER BUSES AND
  REGISTERS
• CONTROL UNIT INTERFACE
• I / O PORTS
• PHYSICAL DATA PATH SYNTHESIS

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CONTROL SYNTHESIS

• SYNTHESIS OF THE CONTROL UNIT
• LOGIC MODEL SYNCHRONOUS FINITE STATE MACHINES
• PHYSICAL IMPLEMENTATION
• PLA , PAL
• ROM

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EXAMPLE OF FSM
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PLA AND PAL

• SET OF AND OR GATES
• PAL -- PGROGRAMMABLE AND OR GATES
• PAL PROGRAMMABLE AND ARRAY FIXED OR ARRAY

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• EXAMPLE OF A PLA

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• THANK YOU !