FPIX2 for FP420

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FPIX2 for FP420?

• David Christian
• April 26, 2005

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FPIX2 at a glance

• Designed to be the BTeV pixel chip.
• 50m x 400m pixels (like ATLAS).
• 22 columns x 128 rows.
• Designed to tile chips in one line with 600m long
  pixels between chips not designed to tile two
  lines of chip on one sensor module.
• High speed, zero suppressed readout.
• Can be 30ns/hit.
• All chips read out in parallel on point-to-point
  links.
• NO TRIGGER.
• Easy to use.
• One bias voltage (2.5V)
• All LVDS I/O No other ASICs required.

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FPIX2 Block Diagram
Pixel Unit Cells (22 columns of 128 rows each)
Core
Fabricated by TSMC (through MOSIS). Only bias
voltages required are 2.5V ground. All I/O is
LVDS.
End-of-Column logic (22 copies)
Core Logic
DACs
Next Word Block
Clock Control Logic
Data Output Interface
Programmable Registers
Word Serializer
Programming Interface
Steering Logic
Data Output Clock
BCO Clock
Input/Output
High Speed Output
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FPIX2 Layout
Debugging Outputs
Pixel array End-of-Column Logic e Core
128x22 Pixel array
End-of-Column Logic
Registers and DACs
Data Output Interface
Command Interface
LVDS Drivers and I/O pads
Internal bond pads for Chip ID
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Pixel Unit Cell
Column Bus
3 bit FADC
Amplifier
Pulse ht 02
Vdda
Ifb
Binary Encoder Register
Token Out
-

Vfb2
Vff
Token Bus Controller
Row 07
Command Interpreter 4 pairs of lines, 4 commands
each Latch Data Output Data Idle
Reset
Sensor
Inject
Token In
Test
Vref
Hit
Bias voltages currents are set by DACs.
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Pixel Cells (four 50 x 400 mm cells)
12 µm bump pads
Preamp
2nd stage disc
Kill/ inject
ADC encoder
Digital interface
ADC
(Top metal layer not shown)
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Status Plans

• Final submission of FPIX2 end of May 05.
• Fixes two fatal flaws in current chips.
• Expect chips back in August September.
• Will construct modules using BTeV sensors
• Tesla moderated p-spray sensors, VTT solder bump
  bonds
• 8x, 6x, 5x, 4x, 1x
• Expect modules Feb. 06
• Plan bench tests beam tests of modules before
  and after irradiation.
• Tests will run through fall 06.

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Possible use for FP420

• Study how fast the BCO clock can go.
• Designed for 7.5 MHz (132 nsec).
• Will probably NOT work at 40 MHz.
• May work at 20 MHz.
• 50ns time resolution?
• Could bond FPIX2s to other detectors and compare
  to BTeV silicon modules.