SRAM Leakage Suppression by Minimizing Standby Supply Voltage

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SRAM Leakage Suppression by Minimizing Standby
Supply Voltage

• Huifang Qin, Yu (Kevin) Cao, Dejan Markovic,
• Andrei Vladimirescu, and Jan Rabaey
• Berkeley Wireless Research Center,
• University of California, Berkeley

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Outline

• Motivations
• SRAM leakage suppression for ultra-low power
  applications
• Exploring Ultra-Low Voltage (ULV) SRAM operation
  capability
• Modeling
• The SRAM Data Retention Voltage (DRV)
• Design and Implementation
• Dual-rail leakage suppression scheme with
  ultra-low standby Vdd
• Measurement Results and Analysis
• To Minimize the SRAM DRV
• Conclusion and Future Work

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Motivation I Leakage Suppression of Embedded SRAM

• Nowadays the embedded SRAM circuits in a
  microprocessor system typically consumes
• 90 of the total processor transistor count
• 60 of the chip area
• 20 50 of chip power

• 100 of ULP system leakage power?

• Power-efficient design is critical for portable
  electronics
• To extend battery life requires maximum power
  savings. Even more demanding is to enable energy
  scavenging

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Motivation I Leakage Suppression of Embedded SRAM

• The situation is further exaggerated by scaling
• 7.5X leakage increase for each technology
  generation
• The ever-increasing process variations make
  things even worse.

• Embedded memory leakage suppression is both
  crucial and effective for deep sub-micron ultra
  low power, low duty cycle system design.

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Motivation II Exploring Low Voltage SRAM
Operation

• Technology driven
• Effectively reduces
• design power
• consumption

Vdd scaling most effective approach in achieving
ultra-low power design.
Question What is the SRAM capability for ULV
operation?
(Figure courtesy of Intel)
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The Simple Scheme SRAM in Ultra-Low Vdd Standby
Goal of the Scheme Minimize standby
leakage power Robust preservation of
memory content

• More to find out
• What is the Data Retention Voltage (DRV) of SRAM?
• How to model DRV from process parameters?
• Any effective way to do DRV-optimized design?

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Look Around Existing Approaches for Low Leakage
SRAM

• Circuit level
• Dynamic control of Gate-Source and
  Substrate-Source Vbias
• Large design and area overhead
• Limited saving on leakage power
• Micro-architectural level
• Vdd gating off for idle memory sections
• Ineffective for caches with large utilization
  ratio
• Drowsy cache put inactive cache lines in a low
  voltage standby mode
• Achieves over 70 leakage energy saving in a data
  cache
• Question to be answered how deep a snap can it
  be?

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Look Around What is Unique in This Work

• A thorough study of ULV SRAM data retention
  behavior
• An effective leakage suppression standby scheme
  for ULP applications
• The whole SRAM is put in standby mode
• Maximum leakage saving and minimum design overhead

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The Data-Retention Voltage (DRV) of SRAM
DRV Condition

• When Vdd scales down to DRV, the Voltage Transfer
  Curves (VTC) of the internal inverters degrade to
  such a level that Static Noise Margin (SNM) of
  the SRAM cell reduces to zero.

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Modeling SRAM DRV

• Coefficients extracted from transistor
  characterizations, such as Vthi, ni, I0i.
• Model can be used for DRV-aware SRAM design
  optimizations

Modeled and simulated DRV as a function of
transistor width scaling.
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Design of Dual-Rail SRAM Standby Scheme
Designed for ULP system

• Standby Vdd noise margin
• 100mV Guard band over DRV gives 55mV W.C. SNM
• Delay overhead
• A 200µm wide PMOS power switch wakes up the
  memory in within 10ns
• Wake up power overhead
• Minimum standby time for positive power saving
  estimated to be around tens of µs.

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Switch Capacitor (SC) Converter Design

• Compared to magnetic-based voltage regulators
• Higher efficiency
• Smaller current ripple
• Easier on-chip integration

• Optimized SC converter design achieves 85 power
  efficiency with 1V input and estimated output load

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4KB SRAM Leakage Control Scheme Test Chip
Standby supply voltage regulator design
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SRAM DRV Measurement
SRAM DRV test suite
Waveform of DRV measurement (a)
DRV 190mV in SRAM cell 1 with state 1
(b) DRV 180mV in SRAM cell 2 with state 0
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SRAM Measurement Results

• More than 90 reduction in leakage power with
  350mV standby Vdd (100mV guard band).

• Measured DRV 80mV 250mV
• (0.13 mm CMOS, 300mV Vth)

• Storage requirement sets Vdd lower limit at
  250mV without error tolerant design

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Analysis What affects SRAM DRV

• Process variation (?L, ?Vth)
• Chip temperature
• SRAM cell sizing

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Resize SRAM Cell for Optimum DRV

• Current sizing
• Performance optimized
• Provides poor DRV

• To optimize for DRV
• Change P/N ratio
• Smaller NMOS
• Larger PMOS

DRV vs. Transistor size Tuning
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DRV-Aware SRAM Cell Sizing Optimization (NMOS)

• By sizing NMOS (W/L) smaller, DRV mean value can
  be reduced by 2030mV.

• (30 delay increase 50 leakage power
  reduction)

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Conclusions and Current Work

• SRAM DRV modeled and silicon-verified
• DRV from 80mV to 250mV for 0.13µm technology,
  300mV Vth.
• DRV model facilitates optimization for ULP SRAM
  design
• Dual-rail standby scheme saves over 90 Pleakage
• Effective and low-cost approach for ULP
  applications
• DRV can be minimized by
• Effective control on process variations ()
• Avoid high temperature operation ()
• SRAM cell sizing optimization at tradeoffs with
  speed and area ()
• Can we further bring down the SRAM Vdd?
• A fix at the architecture level may be more
  effective use error correction schemes to
  tolerate ULV errors