Low Voltage Sensing Techniques for HighSpeed OnChip Interconnects and Caches

1
Low Voltage Sensing Techniques for High-Speed
On-Chip Interconnects and Caches

• Manoj Sinha
• Advisor Prof. Wayne Burleson
• Department of Electrical and Computer Engineering
• University of Massachusetts Amherst

This research work is fully funded by SRC under
Task ID 766.001
Acknowledgements Dr. Ram Krishnamurthy, Dr.
Atila Alvandpour, Dr. Dinesh Somasekhar, Andrew
Laffely, Saurabh Chheda, Atul Maheshwari
2

Outline

• Introduction Problem with interconnects
• Current Sensing for Global Wires
• Secondary Design Issues for Current Sensing
• Secondary Design Issues for Charge Transfer
  Sensing
• Conclusions

3
Problems with Future Interconnects
In
Out
In2
Distributed R, L and C load
In1
Driver
Receiver

• Signaling over global wires and cache bit-lines.
• Increased delay due to large parasitics
• Increased power dissipation due to large
  capacitance
• Signal integrity and noise issue
• Technology scaling worsens the problem by
  increasing
• Resistance
• Capacitance
• Inductance

4
Design Parameters
5
Voltage Mode Repeaters for Global Wires
Receiver
Uniform Repeater Insertion for Interconnect

• Classical solution is repeater insertion at
  regular interval
• Makes the quadratic dependence of delay on line
  length to linear
• Delay of the interconnect is optimum when
• Delaywire Delay Repeater
• Ismail and Friedmans closed form expression used
  for repeater insertion

6
Single-Ended Current Sensing

• Single-ended sensing.
• Transistor M5 provides low-impedance path.
• Driver pushes current into INT or pulls current
  out of INT.
• Current direction sense circuit reacts to the
  changing stimuli, with M3 and M4 providing
  positive feedback.
• Differential amplifier converts the signal into
  CMOS logic level.
• SEL can be used to shut down the circuit to
  prevent static power dissipation.

Current Direction Sense circuit
Differential Amplifier
M. Izumikawa M. Yamashina, A Current Direction
Sense Technique for Multi-Port SRAMs, IEEE
JSSC, April 1996
7
Modified Current Direction Sense Circuit

• NMOS transistors (M1 and M2) are replaced by PMOS
  transistors.
• Modified Current Direction Sense Circuit (MCDS)
  would outperform the original circuit due to
• Increased voltage swing
• Increased current capability
• Differential amplifier is removed by sizing the
  Mod CDS.

8
Experimental Set Up

• Global wire model and device model obtained from
  Berkeley Predictive Technology Model (BPTM) for
  100nm CMOS technology.
• Simulations carried out for Ioff corner at 110C.
• Low- Vt devices with 10x leakage current.
• Voltage mode repeater inserted for very long line
  (gt 5mm) for current sensing.
• Voltage mode repeaters used for long lines in
  current sensing
• Results in increased signal integrity and speed
  benefit.
• Results in scalable switching power

9
Delay Comparison

• MCDS is faster than voltage mode technique by
  13-18.
• Single-ended current sensing doesnt need any
  repeater till 5mm line length.
• Full-swing aggressor considered for current
  sensing too.

10
Delay Comparison with Repeaters for CM

• For line length gt 6mm, current sensing without
  repeater is slower than voltage mode.
• Current mode repeater proves to be slower than
  the voltage mode technique.
• Voltage mode requires a repeater for every 1mm
  line.
• Current sensing with voltage mode repeater for
  line length gt 6mm is 10-12 faster than voltage
  mode.

11
Power Comparison

• Single-ended current sensing technique consumes
• 21 less power than voltage mode technique for
  2mm line.
• 52 less power than voltage mode technique for
  5mm line.
• The data activity for all the comparison done
  here is 100.
• Static power consumption reduced due to removal
  of differential amplifier.

12
Power Comparison at Different Data Activity

• Single-ended current sensing technique consumes
• 38 less power than voltage mode technique for
  50 data activity for 5mm line.
• 11 less power than voltage mode technique for
  17 data activity for 5mm line.
• Static power consumption reduced due to removal
  of differential amplifier.

13
Power Saving for CM with Driver Sizing

• Single-ended current sensing techniques power
  consumption can be reduced by reducing the driver
  size
• Power consumption reduces by 21, when the driver
  size is reduced by 37.
• Delay increases by 5, when the driver size is
  reduced by 37.
• It also reduces the current spikes drawn from
  power supply.

14
Power Saving for CM with Vdd Scaling

• Power can be saved for current sensing by
  reducing Vdd at the driver
• Power consumption reduces by 64, when Vdd is
  reduced from 1.2V to 0.8V.
• Delay increases by 19.8, when the supply voltage
  is reduced by 33.
• CM receiver converts the low-swing signal back to
  normal CMOS logic level.

15
Other Secondary Design Issues

• Supply Voltage Variation
• For CM there is a delay variation of 5 for 20
  variation in Vdd
• For VM there is a delay variation of 7 for 20
  variation in Vdd
• Threshold voltage mismatch doesnt have any
  significant impact on current mode receiver.
• Delay varies less than 3, for a ? Vt 50mV
• Current mode receiver is robust to threshold
  voltage mismatch as
• Large voltage swing
• Differential amplifier is replaced by an inverter

16
Single-Ended Current Sensing vs. Voltage Sensing

• Current sensing is typically faster than voltage
  mode repeaters by 13-18 for line length 2-5mm in
  100nm CMOS technology.
• Current sensing consumes less power than the
  voltage mode
• 38 less power than VM for 50 data activity
• 11 less power than VM for 17 data activity
• Current sensing can be used for low-swing
  signaling technique.
• Can save quadratic switching power
• CM circuit converts the low-swing signal to
  normal CMOS level
• Single-ended current sensing is robust to process
  variation
• Threshold voltage mismatch is offset by large
  swing
• Inverter replaced differential amplifier
• Current sensing circuit consumes static power.
• Voltage mode is much more robust to noise.
• For very long line (gt 6mm), CM requires repeaters
  and involves co-design of voltage mode and
  current sensing.

17

Outline

• Introduction Problem with interconnects
• Current Sensing for Global Wires
• Secondary Design Issues for Current Sensing
• Secondary Design Issues for Charge Transfer
  Sensing

18
Experimental Set Up for Caches
WL127
WL127out
128 bits word Interconnect M3
128 Memory Cells Interconnect M2
WL1
WL0
BL
BL
Interconnect M2
Ysel
SAout
Pch
SAout
Sense Amplifier
SAen
Bit Line Architecture used for Simulations
19
Design Issues of Current Sensing for Caches

• Iso glitch noise delay comparison
• Effect of MUX resistance on current sensing
• Effect of worst case Vt mismatch on modified CMSA
• Other design concerns
• Noise analysis
• Effect of bit-line capacitance on modified CMSA

20
Modified Current Sense Amplifier
Bl
Bl
Pch
Int
Int
Ysel
Pch
I2
I1
sa
sa
B
A
SAen
M1
21
Waveforms Showing Glitch Noise
Glitch Noise 80mV
CURRENT MODE
CURRENT MODE
Glitch Noise 260mV

• Glitch noise for modified CMSA is much higher
  than the VMSA
• Glitch noise should at least be lower than the
  minimum threshold voltage for a process.

22
Iso-Glitch Noise Delay Comparison

• Glitch noise for modified CMSA is fixed by
  inserting additional inverter
• Total area for modified CMSA and VM SA are kept
  the same
• Modified CMSA is 10-13 faster than the VM SA

23
Effect of MUX Resistance on Current Sensing

• The high resistance of column MUX is one of the
  main limitation to the speed of current-sensing
  amplifiers.
• The speed improves by about 10, just by reducing
  the MUX transistor length from 110nm to 100nm.

24
Effect of Worst Case Vt Mismatch

• NMOS stacking in modified CMSA makes it more
  vulnerable to Vt mismatch.
• Sharp increase in modified CMSA delay for ?Vt gt
  10mV
• Two pairs of NMOS transistors are mismatched for
  modified CMSA
• Single pair of NMOS transistors for VM SA.

25
Other Secondary Design Issues

• Modified CMSA is less sensitive to an increase in
  the bit-line capacitance
• Modified CSA speed advantage increases from 13.6
  to 19.6, when the number of cells is tripled.

• Noise Injection
• For a fixed pulse injected on one of the
  bit-lines
• Modified CMSA delay increased by 22.
• VM SA delay increased by 53.
• Injected charge is removed faster for modified
  CMSA as it presents a low-impedance current path.

26

Outline

• Introduction Problem with interconnects
• Current Sensing for Global Wires
• Secondary Design Issues for Current Sensing
• Secondary Design Issues for Charge Transfer
  Sensing

27
Design Issues of Charge Transfer Sensing

• Iso glitch noise delay comparison
• Effect of worst case Vt mismatch on CTSA
• Effect of multiplexer resistance on CTSA delay
• Other design concerns
• Effect of increasing MUXing on CTSA delay
• Effect of bias voltage variation on CTSA delay

28
Charge Transfer SA (CTSA) Operation
bl
bl

• Pre-Charge Phase
• When SAen is high, the output of the common gate
  amp.(M1, M3 M5) is low.
• Vb 0.6V for the simulations.

x 3
Ysel
x 3
Pch
A
B
Pch

• Evaluation Phase
• CTSA is fired by pulling SAen low.
• One PMOS (M1/M2) goes into deep-sub threshold
  region, when one of the bit-line reaches approx.
  Vb Vtp.
• The other bit-line charges the output of the
  common gate amp to Vdd.
• NMOS M10 M11 helps is rejecting the common
  noise initially.

C
D
SAen
M3
M4
Sa
Sa
M5
M10
M11
SAout
29
Delay Comparison with Glitch Fixed

• Glitch noise is fixed by inserting an additional
  inverter.
• CTSA is faster than VM SA by 12-15 for iso -
  glitch noise.

30
Worst Case Vt Mismatch

• Vt mismatched transistors
• 2 pairs of transistors in CTSA
• 1 pair of transistor in VM BKM SA
• For iso-noise with ?Vt 15mV
• CTSA delay increases by 5
• VMSA delay increases by 5.

• Vt mismatched transistors
• 1 bias PMOS 1 sense amp enable PMOS (2 pairs).
• 1 pair of transistor in VM SA
• For ?Vt 15mV
• CTSA delay increases by 5
• VM SA delay increases by 6.

31
Effect of MUX on Delay

• For 15 MUX width variation
• VM SA delay increases by 3.1.
• CTSA delay reduces by 0.8.

• For an increase in MUXing from 41 to 81
• VM SA delay increases by 9.6.
• CTSA delay reduces by 1.5.

32
Other Secondary Design Issues

• For Vt variation of 0-20mV of biased PMOS
• CTSA delay increases by 2.5.
• CTSA glitch noise increased by more than 45 for
  this range.

142mV
127mV
114mV
103mV

• CTSA delay is relatively insensitive to the bias
  voltage variation
• Delay changes by 12, for a change of 20 in bias
  voltage of common gate PMOS.
• Glitch noise changes by 22 for the same case.

33
Conclusions

• Current Sensing techniques shows potential for
  high speed operation.
• Modified Current SA is typically faster than VM
  SA by at least 10-12 for similar glitch noise.
• Current mode SA speed is limited by the high
  resistance of the column MUX.
• The sense amp speed improved by 10 with the
  reduction in MUX length.
• Current Sensing techniques gives a 35-40 lower
  bit-line swing as compared to VM SA.
• Saves quadratic energy required to charge and
  discharge the bit line.
• Current Sensing is less sensitive to an increase
  in the bit-line capacitance.
• Maintaining bit-line voltage close to power
  supply voltage may contribute to large noise
  margin of memory cell.
• Current Sensing is vulnerable to Vt mismatch.
• Current Sensing speed is limited by the high
  resistance of column multiplexer.

34
Conclusions Continued

• CTSA offers an speed advantage of approx. 12-15
  over VM SA for iso-glitch noise.
• CTSA is very efficient in terms of energy
  consumption
• Bit line swing is reduced by 18-20.
• There is an energy saving of 30 over VM.
• CTSA is as robust as VM SA with Vt variation and
  bit-line capacitance mismatch.
• CTSA gives another degree of freedom in the
  design of column multiplexer.
• CTSA delay reduces by 1.5 when the multiplexing
  is increased from 41 to 81.
• VMSA delay increases by 9.6 for the same.
• CTSA suffers from additional complexity in the
  design of bias voltage generator.
• CTSA also suffers from speed limitation due to
  the high resistance of the column MUX.

35
Publications and Disclosures

• M. Sinha and W. Burleson, Current-Sensing for
  Crossbars, in IEEE International Conference on
  ASIC/SOC 2001.
• M. Sinha, A. Maheshwari and W. Burleson,
  Low-Swing Single-Ended Current-Sensing for High
  Performance and Low Power Design, a Technical
  report submitted to SRC July 2001.
• M. Sinha, A. Alvandpour, W. Burleson and R.
  Krishnamurthy, Low-Voltage Sense Amplifier for
  sub-100nm Caches, to be submitted to CICC 2003.
• Filed an invention disclosure for Differential
  Current Sense Amplifier for Caches, with Intel
  Corporation.
• Filed an invention disclosure for Charge
  Transfer Sense Amplifier for Caches, with Intel
  Corporation

36
Thank you all!
37
Modified CSA Delay for Different Glitch Noise
82mV
92mV
104mV
110mV
126mV

• Modified CSA delay improves by 6.5, when the
  glitch noise increases from 82mV to 126mV.
• Modified CMSA is 16 faster than the VM SA, when
  the glitch noise of modified CMSA is 104mV.

38
Effect on SA operation due to mismatch

• Delay increases by 6 for CTSA and 10 for VM for
  ?Vt 25mV

• CTSA is more robust for bit-line capacitance
  mismatch(0- 40) in terms of delay.
• Delay increases by 3.3 for CTSA and 6.5 for VM.
• Glitch noise increases by 15 for both CTSA and
  VM.

39
Current Mode Voltage Mode Circuits
SAout
SAen
Voltage Mode Sense Amplifier
40
Proposed Work

• Repeater insertion for long interconnects.
• Impact of technology scaling for voltage mode and
  current mode technique.
• Increased leakage current.
• Exponential increase in the number of repeaters.
• Secondary design issues for interconnects
• Modeling of inductance.
• Power supply noise.
• Effect of MUX resistance on current sensing
  technique speed for caches.
• Current sensing insensitivity to bit-line
  capacitance.
• Secondary design issues of current sensing for
  caches
• Effect of orthogonal noise injection.
• Effect of bit-line capacitance mismatch.
• Threshold voltage mismatch of sense amplifier.
• Iso-glitch noise comparison of all the sensing
  techniques.

41
Continued

• Effect of multiplexing on charge transfer sensing
  technique.
• Worst case threshold voltage mismatch.
• Impact of bias voltage variation on
• CTSA delay
• Functionality, when there exists a difference in
  bias voltage.