III. Multicore Processors (5)

1
III. Multicore Processors (5)

• Dezso Sima
• Spring 2007

(Ver. 2.0)
? Dezso Sima, 2007
2
10.3 IBMs MC processors

• 10.3.1 POWER line

• 10.3.2 Cell BE

3
10.3 IBMs MC processors
10.3.1 POWER line

• POWER4

180 nm
10/2001
130 nm

• POWER4

11/2002

• POWER5

130 nm
5/2004
90 nm

• POWER5

10/2005
65 nm

• POWER6

2007
4
10.3.1 Evolution of IBMs major RISC lines
Figure The evolution of IBMs major RISC lines
5
10.3.1 POWER4 (1)
Service Processor
Core interface Unit (crossbar)
Power On Reset
Built-In-SelfTest
Non-Cacheable Unit
MultiChip Module
Figure POWER4 chip logical view
Tendler, J.M., Dodson, S., Fields S., Le H.,
Sinharoy B. Power4 System Microarchitecture,,
IBM J. Res. Dev. Vol. 46, No. 1, Jan.
2002, pp. 5-25, http//www.research.ibm.com/journ
al/rd/461/tendler.pdf
6
10.3.1 POWER4 (2)
Figure Logical view of the L3 controller
Source Power4 System Microarchitecture,
Technical White Paper, 2001, IBM Corp.,
http//www-03.ibm.com/servers/eserver/pseries/ha
rdware/whitepapers/power4.pdf
7
10.3.1 POWER4 (3)
Figure The memory cotroller of the POWER4
Source Power4 System Microarchitecture,
Technical White Paper, 2001, IBM Corp.,
http//www-03.ibm.com/servers/eserver/pseries/ha
rdware/whitepapers/power4.pdf
8
10.3.1 POWER4 (4)
Fabric Controller
Figure I/O controller of the POWER4
Source Power4 System Microarchitecture,
Technical White Paper, 2001, IBM Corp.,
http//www-03.ibm.com/servers/eserver/pseries/ha
rdware/whitepapers/power4.pdf
9
10.3.1 POWER4 (5)
Figure POWER4 chip
Source R. Kalla, B. Sinharoy, J. Tendler
Simultaneous Multi-threading Implementation in
Power5 IBMs Next Generation POWER
Microprocessor, 2003 http//www.hotchips.org/archi
ves/hc15/3_Tue/11.ibm.pdf
10
10.3.1 POWER4 (6)
1 SMC Single Chip Module 2 MCM Multi Chip
Module 3 DCM Dual Chip Module
4 DCM Dual Core Module 5 QCM Quad Core Module 6
DPM Dynamic Power Management
Table Main features of IBMs dual-core POWER line
11
10.3.2 POWER4 (1)
Figure New features of the POWER5
Source Grassl C., New IBM Components for HPCx,
Dec. 2003, http//www.hpcx.ac.uk/about/events/ann
ual2003/Grassl.pdf
12
10.3.1 POWER4 (2)
1 SMC Single Chip Module 2 MCM Multi Chip
Module 3 DCM Dual Chip Module
4 DCM Dual Core Module 5 QCM Quad Core Module 6
DPM Dynamic Power Management
Table Main features of IBMs dual-core POWER line
13
10.3.1 POWER5 (1)
Figure 5.14 Contrasting POWER4 and POWER5 system
structures
SourceBarney B., IBM POWER Systems Overview,
Livermore Computing, 2006, http//www.llnl.gov/co
mputing/tutorials/ibm_sp/
14
10.3.1 POWER5 (2)
Figure Block diagram of the POWER5 (1)
SourceBarney B., IBM POWER Systems Overview,
Livermore Computing, 2006, http//www.llnl.gov/co
mputing/tutorials/ibm_sp/
15
10.3.1 POWER5 (3)
Figure Block diagram of the POWER5 (2)
http//studies.ac.upc.edu/ETSETB/SEGPAR/microproce
ssors/power520(2)20(mpr).pdf
16
10.3.1 POWER5 (4)
Figure Floorplan of the POWER5
Source Shinharoy B., Kalla R.N., Tendler J.M.,
Eickenmeyer R.J., Joyner J.B., POWER5 system
microarchitecture, IBM J. RD, Vol. 49,
No. 4/5, 2005, pp. 505-521
17
10.3.1 POWER5 (6)
POWER5
POWER4
180 nm, 412 mm2
130 nm, 389 mm2 (enlarged)
Figure Contrasting the floor plans of the POWER4
and POWER5 dies
Sources R. Kalla, B. Sinharoy, J. Tendler
Simultaneous Multi-threading Implementation in
Power5 IBMs Next Generation POWER
Microprocessor, 2003http//www.hotchips.org/archiv
es/hc15/3_Tue/11.ibm.pdf
Shinharoy B., Kalla R.N., Tendler J.M.,
Eickenmeyer R.J., Joyner J.B., POWER5 system
microarchitecture, IBM J. RD, Vol. 49,
No. 4/5, 2005, pp. 505-521
18
10.3.1 POWER5 (7)
POWER5 Dual-Core Module
Figure Packaging alternatives of the POWER4/5
processors
Source Partridge R. and Ghatpande S., IBM
Introduces POWER5 and Quad-Core Modules in
System p5, Tech Trends Monthly,
Nov./Dec. 2005,
19
10.3.1 POWER5 (8)
POWER4 MCM Photo 32-way System Showing 4 MCMs and L3 Cache
                                                                                                                    


Figure QuadChip POWER4 module (MCM) and a
32-way POWER4 system
SourceBarney B., IBM POWER Systems Overview,
Livermore Computing, 2006, http//www.llnl.gov/co
mputing/tutorials/ibm_sp/
20
10.3.1 POWER5 (9)
Figure Interpretation of Dual-Chip Modules
(DCMs) and Multi-Chip Modules (MCM) of the POWER5
SourceBarney B., IBM POWER Systems Overview,
Livermore Computing, 2006, http//www.llnl.gov/co
mputing/tutorials/ibm_sp/
21
10.3.1 POWER5 (10)
Figure Photos of Dual-Chip Modules (DCMs) and
Multi-Chip Modules (MCM) of the POWER5
SourceBarney B., IBM POWER Systems Overview,
Livermore Computing, 2006, http//www.llnl.gov/co
mputing/tutorials/ibm_sp/
22
10.3.1 POWER5 (11)
Figure The Multi-chip module of the POWER5
Source Kalla R., IBMs POWER5 Microprocessor
Design and Methodology, 2003, www-csl.csres.utexa
s.edu/users/billmark/teach/cs352-05-spring/lecture
s/Lecture22-RonKallaIBM.pdf
23
10.3.1 POWER5 (12)
POWER5
POWER4
POWER4
POWER line
DC
DC
DC
Dual/Quad-Core
5/2004
11/2002
10/2001
Introduced
130 nm
130 nm
180 nm
Technology
389 mm2
380 mm2
412 mm2
Die size
276 mtrs
184 mtrs
174 mtrs
Nr. of transistors
1.65/1.9
1.7
1.3
fc GHz
L2
1.9 MB/shared
1.5 MB/shared
1.44 MB/shared
Size/allocation
On-chip
On-chip
On-chip
Implementation
L3
36 MB
32 MB
32 MB
Size
Tags on-chip, data off-chip
Implementation
On-chip
On-chip
Off-chip
Mem. contr.
80 (est)
70
115/125
TDP W
DCM3/MCM2
SCM1/MCM2
SCM1/MCM2
Packaging
Dual threaded
DPM6
Power management
Tags on-chip
Tags on-chip
L3 impl.
36 MB
32 MB
L3 size
1 SMC Single Chip Module 2 MCM Multi Chip
Module 3 DCM Dual Chip Module
4 DCM Dual Core Module 5 QCM Quad Core Module 6
DPM Dynamic Power Management
Table Main features of IBMs dual-core POWER line
24
10.3.1 POWER5 (1)
Figure Block diagram of the POWER5
Source Vetter S. et al., IBM System p5 Quad-Core
Module Based on POWER5 Technology, Redbooks
paper, IBM Corp. 2006, http//www.redbooks.ibm.c
om/redpapers/pdfs/redp4150.pdf
25
10.3.1 POWER5 (2)
Figure Dual-Core Modules (DCMs) and Quad-Core
Modules (QCM) of the POWER5
Source Vetter S. et al., IBM System p5 Quad-Core
Module Based on POWER5 Technology, Redbooks
paper, IBM Corp. 2006, http//www.redbooks.ibm.c
om/redpapers/pdfs/redp4150.pdf
26
10.3.1 POWER5 (3)
10.3
1 SMC Single Chip Module 2 MCM Multi Chip
Module 3 DCM Dual Chip Module
4 DCM Dual Core Module 5 QCM Quad Core Module 6
DPM Dynamic Power Management
Table Main features of IBMs dual-core POWER line
27
10.3.1 POWER6 (1)
POWER6
POWER5
Hardware support of decimal arithmetic
Figure Contrasting the block diagrams of the
POWER5 and POWER6 processors
Source Kanter D., IBM Previews the Power6,
Oct. 2006, dkanter_at_realwordtech.com
28
10.3.1 POWER6 (2)
1 SMC Single Chip Module 2 MCM Multi Chip
Module 3 DCM Dual Chip Module
4 DCM Dual Core Module 5 QCM Quad Core Module 6
DPM Dynamic Power Management
Table Main features of IBMs dual-core POWER line
29
10.3 IBMs MC processors
10.3.2 Cell BE

• Cell BE

90 nm
2/2006
30
10.3.2 Cell BE (1)
Figure The history and development cost of the
Cell BE
Sources Brochard L., A Cell History, Cell
Workshop, April, 2006
http//www.irisa.fr/orap/Constructeurs/Cell/Cell2
0Short20Intro20Luigi.pdf

Hofstee H. P., Cell today and tomorrow,
2005, http//www.stanford.edu/class/ee380/Abstrac
ts/Cell_060222.pdf
31
10.3.2 Cell BE (2)
AUC Atomic Update Cache BIC Bus Interface
Contr. EIB Element Interface Bus LS Local
Store of 256 KB MFC Memory Flow Controller MIC
Memory Interface Contr. PPE Power Processing
Element PXU POWER Execution Unit SMF
Synergistic Memory Flow Unit SPU
Synergistic Processor Unit SXU Synergistic
Execution Unit XDR Rambus DRAM
Figure Block diagram of the Cell BE
Source Gshwind M., Chip Multiprocessing and the
Cell BE, ACM Computing Frontiers, 2006,
http//beatys1.mscd.edu/compfront//2006/cf06-g
schwind.pdf
32
10.3.2 Cell BE (3)
Design parameters of the Cell BE
PPE dual-threaded gt 200 GFLOPS (SP) gt 20
GFLOPS (DP) gt 25 GB/s memory BW gt 75 GB/s I/O
BW gt 300 GB/s EIB BW fc gt 4 GHz (lab)
Figure Main design parameters of the Cell BE
Source IBM Cell Broadband Engine Overview,
Course Code L1T1H1-02, Mai 2006
publib.boulder.ibm.com/.../stgv1r0/topic/com.ibm.i
ea.cbe/cbe/1.0/Overview/L1T1H1_02_CellOverview.pdf

33
10.3.2 Cell BE (4)
Figure 5.16 Cell SPE architecture
Source Blachford N. Cell Architecture
Explained Version 2,
http//www.blachford.info/computer/Cell/Cell1_v2.h
tml
34
10.3.2 Cell BE (5)
Figure Block diagram of the SPE
Source Gshwind M., Chip Multiprocessing and the
Cell BE, ACM Computing Frontiers, 2006,
http//beatys1.mscd.edu/compfront//2006/cf06-g
schwind.pdf
35
10.3.2 Cell BE (6)
Figure Pipeline stages of the Cell BE
Source Gshwind M., Chip Multiprocessing and the
Cell BE, ACM Computing Frontiers, 2006,
http//beatys1.mscd.edu/compfront//2006/cf06-g
schwind.pdf
36
10.3.2 Cell BE (7)
Figure Floor plan of a single SPE
Source Gshwind M., Chip Multiprocessing and the
Cell BE, ACM Computing Frontiers, 2006,
http//beatys1.mscd.edu/compfront//2006/cf06-g
schwind.pdf
37
10.3.2 Cell BE (8)
Principle of operation of the Element Interface
Bus (EIB)
Source Keable C., And we also have hardware...
17th Machine Evaluation Workshop, Dec. 2006,
http//www.cse.clrc.ac.uk/disco/mew17/talk
s/Keable_IBM_MEW17.pdf
38
10.3.2 Cell BE (9)
Figure The Element Interface Bus EIB)
Source Gshwind M., Chip Multiprocessing and the
Cell BE, ACM Computing Frontiers, 2006,
http//beatys1.mscd.edu/compfront//2006/cf06-g
schwind.pdf
39
10.3.2 Cell BE (10)
Figure The Synergistic Memory Flow unit (SMF)
Source Gshwind M., Chip Multiprocessing and the
Cell BE, ACM Computing Frontiers, 2006,
http//beatys1.mscd.edu/compfront//2006/cf06-g
schwind.pdf
40
10.3.2 Cell BE (11)
235 mm2 241 mtrs
Figure Floor plan of the Cell BE processor
Source Gshwind M., Chip Multiprocessing and the
Cell BE, ACM Computing Frontiers, 2006,
http//beatys1.mscd.edu/compfront//2006/cf06-g
schwind.pdf
41
10.3.2 Cell BE (12)
Table Main features of the IBMs Cell BE
42
10.3.2 Cell BE (13)
Figure Cell BE Blade Roadmap
Source Brochard L., A Cell History, Cell
Workshop, April, 2006
http//www.irisa.fr/orap/Constructeurs/Cell/Cell2
0Short20Intro20Luigi.pdf
43
10.3.2 Cell BE (14)
Figure Roadmap of the Cell BE
Source Hofstee H. P., Real-time Superconputing
and Technology for Games and Entertainment,
2006, http//www.cercs.gatech.edu/doc
s/SC06_Cell_111606.pdf
44
10.3 Literature (1)
POWER4, POWER4
Barney B., IBM POWER Systems Overview,
Livermore Computing, 2006,
http//www.llnl.gov/computing/tutorials/ibm_sp/
DeMone P., Sizing Up the Super Heavyweights,
Real Word Technologies, Sept. 2004,
http//h21007.www2.hp.com/dspp/files/unprotected/I
tanium/sizingsuperheavys.pdf
Grassl C., New IBM Components for HPCx, Dec.
2003, http//www.hpcx.ac.uk/about/events/annual20
03/Grassl.pdf
Krevell K., IBMs POWER4 Unveiling Continuues,
Microprocessor Report, Nov. 20. 2000, pp- 1-4
Tendler, J.M., Dodson, S., Fields S., Le H.,
Sinharoy B. Power4 System Microarchitecture, IBM
Server, Technical White Paper, October
2001 http//www-03.ibm.coom/servers/eserver/pseri
es/hardware/whitepapers/power4.pdf
Tendler, J.M., Dodson, S., Fields S., Le H.,
Sinharoy B. Power4 System Microarchitecture,,
IBM J. Res. Dev. Vol. 46, No. 1, Jan.
2002, pp. 5-25, http//www.research.ibm.com/journ
al/rd/461/tendler.pdf
POWER5, POWER5
Barney B., IBM POWER Systems Overview,
Livermore Computing, 2006,
http//www.llnl.gov/computing/tutorials/ibm_sp/
DeMone P., Sizing Up the Super Heavyweights,
Real Word Technologies, Sept. 2004,
http//h21007.www2.hp.com/dspp/files/unprotected/I
tanium/sizingsuperheavys.pdf
Grassl C., New IBM Components for HPCx, Dec.
2003, http//www.hpcx.ac.uk/about/events/annual20
03/Grassl.pdf
Kalla R., IBMs POWER5 Microprocessor Design and
Methodology, 2003, www-csl.csres.utexas.edu/user
s/billmark/teach/cs352-05-spring/lectures/Lecture2
2-RonKallaIBM.pdf
45
10.3 Literature (2)
POWER5, POWER5 (cont.)
Kalla R., Sinharoy B., Tendler J. Simultaneous
Multi-threading Implementation in Power5 IBMs
Next Generation POWER Microprocessor,
2003 http//www.hotchips.org/archives/hc15/3_Tue/
11.ibm.pdf
Krevell K., POWER5 Tops on Bandwidth,
Microprocessor Report, Dec. 2003 http//studies.a
c.upc.edu/ETSETB/SEGPAR/microprocessors/power520(
2)20(mpr).pdf
Shinharoy B., Kalla R.N., Tendler J.M.,
Eickenmeyer R.J., Joyner J.B., POWER5 system
microarchitecture, IBM J. RD, Vol. 49,
No. 4/5, 2005, pp. 505-521
Vetter S. et al., IBM System p5 Quad-Core Module
Based on POWER5 Technology, Redbooks paper,
IBM Corp. 2006, http//www.redbooks.ibm.com/re
dpapers/pdfs/redp4150.pdf
POWER6
Kanter D., IBM Previews the Power6, Oct. 2006,
dkanter_at_realwordtech.com
Cell BE
Blachford N. Cell Architecture Explained
Version 2, http//www.blachford.info/comput
er/Cell/Cell1_v2.html
Brochard L., A Cell History, Cell Workshop,
April, 2006 http//www.irisa.fr/orap/Construc
teurs/Cell/Cell20Short20Intro20Luigi.pdf
Day M. and Hofstee P., Hardware and Software
Architectures for the Cell Broadband Engine
processor, CODES, Sept. 2006,
http//www.casesconference.org/cases2005/pdf/Cell-
tutorial.pdf
Gshwind M., Chip Multiprocessing and the Cell
BE, ACM Computing Frontiers, 2006,
http//beatys1.mscd.edu/compfront//2006/cf06-gschw
ind.pdf
46
10.3 Literature (3)
Cell BE (cont.)
Gschwind M., Hofstee H. P., Flachs B. K.,
Hophkins M., Watanabe Y., Yamazaki T
Synergistic Processing in Cell's Multicore
Architecture, IEEE Micro, Vol. 26, No. 2, 2006,
pp. 10-24
Hofstee H. P., Real-time Superconputing and
Technology for Games and Entertainment, 2006,
http//www.cercs.gatech.edu/docs/SC06_Cell_1116
06.pdf
Keable C., And we also have hardware... 17th
Machine Evaluation Workshop, Dec. 2006,
http//www.cse.clrc.ac.uk/disco/mew17/talks/Keable
_IBM_MEW17.pdf
Krolak D., Unleashing the Cell Broadband Engine
Processor, MPR Fall Proc. Forum, Nov. 2005,
http//www-128.ibm.com/developerworks/power/libra
ry/pa-fpfeib/?cadgr-lnxwCellConnects
Krewell K., Cell Moves Into The Limelight,
Microprocessor Report, Febr. 14 2005, pp. 1-9
Solie, D., Technology Trends Presentation,
Power Symposium, Aug. 2006,
http//www-03.ibm.com/procurement/proweb.nsf/objec
tdocswebview/ file14-darrylsolie-ibmpow
ersymposiumpresentation/file/
14-darrylsolie-ibm-powersymposiumpresentation
v2.pdf
- Cell Broadband Engine processor based
systems, White Paper, IBM Corp., 2006