Switching Units

1
Switching Units
2
Types of switching elements

• Telephone switches
• switch samples
• Datagram routers
• switch datagrams
• ATM switches
• switch ATM cells

INPUTS
OUTPUTS
3
Look Inside a Router

• Two key router functions
• run routing algorithms/protocol (RIP, OSPF, BGP)
• switching datagrams from incoming to outgoing
  ports

3
4
Repeaters, bridges, routers, and gateways

• Repeaters/Hubs at physical level (L1)
• Bridges at datalink level (L2)
• based on MAC addresses
• discover attached stations by listening
• Routers at network level (L3)
• participate in routing protocols
• Application level gateways at application level
  (L7)
• treat entire network as a single hop
• Gain functionality at the expense of forwarding
  speed
• for best performance, push functionality as low
  as possible

5
Types of services

• Packet vs. circuit switches
• packets have headers and samples dont
• Connectionless vs. connection oriented
• connection oriented switches need a call setup
• setup is handled in control plane by switch
  controller
• connectionless switches deal with self-contained
  datagrams

6
Other switching unit functions

• Participate in routing algorithms
• to build routing tables
• Next Lecture!
• Resolve contention for output trunks
• buffer scheduling
• Previous Lecture!
• Admission control
• to guarantee resources to certain streams

7
Requirements

• Capacity of switch is the maximum rate at which
  it can move information, assuming all data paths
  are simultaneously active
• Primary goal maximize capacity
• subject to cost and reliability constraints
• Circuit switch must reject call if cant find a
  path for samples from input to output
• goal minimize call blocking
• Packet switch must reject a packet if it cant
  find a buffer to store it awaiting access to
  output trunk
• goal minimize packet loss
• Subgoal Dont reorder packets

8
Internal switching

• In a circuit switch, path of a sample is
  determined at time of connection establishment
• No need for a sample header--position in frame is
  enough
• In a packet switch, packets carry a destination
  field
• Need to look up destination port on-the-fly
• Datagram
• lookup based on entire destination address
• Cell
• lookup based on VCI used as an index to a table
  
• Other than that, switching units are very similar

9
Blocking in packet switches

• Can have both internal and output blocking
• Internal
• no path to output
• Example head of line blocking.
• Output
• output link busy
• If packet is blocked, must either buffer or drop
  it

10
Dealing with blocking

• Overprovisioning
• internal links much faster than inputs
• Buffers
• at input or output
• Backpressure
• if switch fabric doesnt have buffers, prevent
  packet from entering until path is available
• Parallel switch fabrics
• increases effective switching capacity

11
Three generations of packet switches

• Different trade-offs between cost and performance
• Represent evolution in switching capacity, rather
  than in technology
• With same technology, a later generation switch
  achieves greater capacity, but at greater cost
• All three generations are represented in current
  products

12
First generation switch
computer
CPU
queues in memory
linecard

• Most Ethernet switches and cheap packet routers
• Bottleneck can be CPU, host-adaptor or I/O bus,
  depending

13
Second generation switch
computer
bus
front end processors or line cards

• Port mapping intelligence in line cards
• Bottleneck is the bus (or ring)

14
Third generation switches

• Third generation switch provides parallel paths
  (fabric)

OLC
ILC
NxN packet switch fabric
OUT
OLC
IN
ILC
OLC
ILC
control
15
Third generation (contd.)

• Features
• self-routing fabric
• output buffer is a point of contention
• unless we arbitrate access to fabric
• potential for unlimited scaling,
• as long as we can resolve contention for output
  buffer

16
Line Cards (for CRS-1)
17
CRS-1 routers
18
Switching - Fabric
19
Switching abstract model
Number of connections from few (4 or 8) to huge
(100K)
20
Multiplexors and demultiplexors

• Multiplexor aggregates sessions
• N input lines
• Output runs N times as fast as input
• Demultiplexor distributes sessions
• one input line and N outputs that run N times
  slower
• Can cascade multiplexors

21
Time division switching

• Key idea when demultiplexing, position in frame
  determines output link
• Time division switching interchanges sample
  position within a frame
• Time slot interchange (TSI)

22
Time Slot Interchange (TSI) example
sessions (1,3) (2,1) (3,4) (4,2)
1 2 3 4
2
1
4
2
3 1 4 2
1
3
3
4
Read and write to shared memory in different order
23
TSI

• Simple to build.
• Multicast easy (why?)
• Limit is the time taken to read and write to
  memory
• For 120,000 telephone circuits
• Each circuit reads and writes memory once every
  125 ms.
• Number of operations per second 120,000 x 8000
  x2
• each operation takes around 0.5 ns gt impossible
  with current technology
• Need to look to other techniques

24
Space division switching

• Each sample takes a different path through the
  switch, depending on its destination
• Crossbar Simplest possible space-division switch
• Crosspoints can be turned on or off

25
Crossbar - example
sessions (1,2) (2,4) (3,1) (4,3)
inputs
output
26
Crossbar

• Advantages
• simple to implement
• simple control
• strict sense non-blocking
• Multicast
• Single source multiple destination ports
• Drawbacks
• number of crosspoints, N2
• large VLSI space
• vulnerable to single faults

27
Time-space switching

• Precede each input trunk in a crossbar with a TSI
• Delay samples so that they arrive at the right
  time for the space division switchs schedule

Crosspoint 4 (not 16) memory speed x2 (not x4)
28
Finding the schedule

• Build a routing graph
• nodes - input links
• session connects an input and output nodes.
• Feasible schedule
• Computing a schedule
• compute perfect matching.

29
Time-Space Example
TSI
Internal speed double link speed
30
Time-space-time (TST) switching

• Allowed to TSI both on input and output
• Gives more flexibility gt lowers call blocking
  probability

31
Internal Non-Blocking Types

• Re-arrangeable
• Can route any permutation from inputs to
  outputs.
• Strict sense non-blocking
• Given any current connections through the
  switch.
• Any unused input can be routed to any unused
  output.
• Wide sense non-blocking.
• There exists a specific routing algorithm, s.t.,
• for any sequence of connections and releases,
• Any unused input can be routed to any unused
  output,
• assuming all the sequence was served by the
  routing algorithm.

32
Circuit switching - Space division

• graph representation
• transmitter nodes
• receiver nodes
• internal nodes
• Feasible schedule
• edge disjoint paths.
• cost function
• number of crosspoints (complexity of AxB is AB)
• internal nodes

33
Crossbar - example
1
2
3
4
4
1
2
3
34
Another Example
inputs
outputs
35
Another Example
sessions (1,3) (2,6) (3,1) (4,4) (5,2) (6,5)
inputs
outputs
36
Clos Network
Clos(N, n , k) N - inputs/outputs
cross-points 2 (N/n)nk k(N/n)2
kxn
nxk
(N/n)x(N/n)
2x2
3x3
N6 n2 k2
2x2
N
3x3
2x2
k
N/n
N/n
37
Clos Network - strict sense non-blocking

• Holds for k ? 2n-1
• Proof Methodology
• Recall IF A,B ? S and AB gt S then An
  B?Ø
• S The k middle switches
• A middle switches reachable from the inputs
• B middle switches reachable from the outputs
• Our case
• Sk
• A k-(n-1)
• B k-(n-1)

38
Clos Network - strict sense non-blocking

• Holds for k ? 2n-1
• Proof
• Consider an idle input and output
• Input box connected to at most n-1 middle layer
  switches
• output box connected to at most n-1 middle layer
  switches
• There exists an unused" middle switch good for
  both.

39
Example
Clos(8,2,3)
Need to route a new call
40
Clos Network
Why is kn internally blocking?
41
Clos Network - re-arrangable

• Holds for k ? n
• Proof
• Consider the routing graph.
• find a perfect matching.
• route the perfect matching through a
• single middle switch!
• remaining network is Clos(N-N/n,n-1,k-1)
• summary
• smaller circuit
• weaker guarantee

42
Recursive Construction basis
The basic element
The dimension r0
The two states
43
Recursive Construction Benes Network
r-1 dimension N/2 size
r-1 dimension N/2 size
44
Example 16x16
45
Benes Networks

• Symmetry
• Size
• F(N) 2(N/2)4 2F(N/2) O(N log N)
• Rearrangable
• Clos network with k2 n2
• Proof I
• Build routing graph.
• Find 2 matchings
• route one in the upper Benes and the other in the
  lower.

46
Greedy permutation routing

• Start with an arbitrary node i1
• set i1 to upper.
• At the output, o1 , a new constraint,
• set o2 to lower.
• Continue until no new constraint.
• Completing a cycle.
• Continue until done.
• Solve for the upper and lower Benes recursively.

47
Example Benes Network for r2
I1
1 2 3 4 5 6 7 8
I2
level 0 switches
level 2r switches
48
Example
1 2 3 4 5 6 7 8 1 5 6 8 4
2 3 7
)
(
I1
1 2 3 4 5 6 7 8
I2
level 0 switches
level 2r switches
49
Example
1 2 3 4 5 6 7 8 1 5 6 8 4
2 3 7
)
(
I1
1 2 3 4 5 6 7 8
I2
level 0 switches
level 2r switches
50
Example
1 2 3 4 5 6 7 8 1 5 6 8 4
2 3 7
)
(
I1
1 2 3 4 5 6 7 8
I2
level 0 switches
level 2r switches
51
Example
1 2 3 4 5 6 7 8 1 5 6 8 4
2 3 7
)
(
I1
1 2 3 4 5 6 7 8
I2
level 0 switches
level 2r switches
52
CRS-1 Switch Fabric Overview
50 Gbps136 Bytes cells
100 Gbps/LC(2)(2.5X Speedup)
Fabric Chassis
40 Gbps
8 of 8
8
16
S1
S2
S3
2 of 8
2
2
1 of 8
1
1
Line Card
Line Card
S1
S2
S3
2 LEVELS OF PRIORITY HP Low latency traffic LP
Best effort traffic
MULTICAST SUPPORT 1M multicast groups
S1
S2
S3
1296 x 1296 buffered non-blocking
switchMulti-stage Interconnect3 Stage Benes
topology
53
Basic Router Architecture
3 Main components Line cards,Switching
mechanism, Route Processor(s), Routing
Applications
Forwarding Component
Interconnect
Control Components
54
Strict Sense non-Blocking
N/2 x N/2
. . .
. . .
N/2 x N/2
N/2 x N/2
55
Properties

• Size
• F(N) 2N6 3F(N/2) O( N1.58 )
• strict sense non-blocking
• Clos network with k3 n2
• Better parameters
• nsqrtN, k2sqrtN-1
• recursive size sqrtN x sqrtN
• Circuit size O(N log2.58 N)

56
Cantor Networks

• m copies of Benes network.
• For m log N its strict sense non-blocking
• Network size N log2 N
• Example

57
Cantor Network
m4
58
Proof Sketch

• Benes network
• 2 log N -1 layers,
• N/2 nodes in layer.
• Middle layer layer log N -1
• Consider the middle layer of the Benes Networks.
• There are Nm/2 nodes in in all of them combined.
• Bound (from below) the number of nodes reachable
  from an input and output.
• If the sum is more than Nm/2
• There is an intersection
• there has to be a route.

59
Proof Sketch

• Let A(k) number of nodes reachable at level k.
• A(0)m
• A(1) 2A(0)-1
• A(2)2A(1)-2
• A(k)2A(k-1) - 2k-1 2k A(0) - k 2k-1
• A(log N -1) Nm/2 - (log N -1) N/4
• Need that 2A(log N -1) gt Nm/2.
• 2Nm/2 - (log N -1) N/4 gt Nm/2.
• Hold for mgt log N-1.

60
Advanced constructions

• There are networks of size O(N log N).
• the constants are huge!
• Basic paradigm also applies to large packet
  switches.