Florian Herrmann

1
First steps towards RPD readout

• Florian Herrmann
• University of Freiburg

2
Who we are
Louis Lauser
Konrad Wenzel
Sebastian Schopferer
3
What we do
COMPASS DAQ
RPD
Readout electronics
for
4
Calculate time amplitude
Amplitude
Time
Task 1 ?Compare gradient and maximum ?If
accurate give time and amplitude to DAQ
5
Selection
Amplitude
Time
Task 2 ?Compare gradient and maximum ?If not
accurate substract pulse shape given by
gradient ?Then do Task 1
6
High Dynamic Range Trigger
Amplitude
1000mV
40mV
Time

• Generate a trigger from the RPD information

7
Requirements for Readout

• What are the requirements for the RPD readout
  electronics?

• High resolution -gt 12 bits

• High sampling rate -gt 1 Gsps

• Powerful logic -gt Digital Signal
• Processing

• Very Fast logic -gt trigger
• generation

8
ENOB

• SNR Signal-to-Noise ratio,SNR 20 log
  (Fundamental / SQRT (SUM (SQR(Noise))))
• THD Total-Harmonic-Distortion,THD 20 log
  (SQRT (SUM (SQR (Harmonics))) / Fundamental)
• SINAD Signal-to-Noise And Distortion,SINAD
  20 log (Fundamental / SQRT (SUM (SQR(Noise
  Harmonics))))
• ENOB How close the ADC solution is near to the
  theoretical mathematical model,where A is the
  input amplitude and V is the full scale range of
  the ADC ENOB (SINAD 1.76)20log(A/(V/2)) /
  6.02

9
Sampling Methods
C.A.E.N V1729
Direct Readout
ADC
FPGA
COMPASS DAQ
10
Interleaved Mode

• Advantage high resolution _at_ high sampling
  rate
• needs
• symmetric PCB Layout
• 2 clock signals (180 phase)
• possible errors
• due to gain mismatch
• due to offset mismatch
• due to clock skew
• Solution

12bit 1Gsps !
ADC
Clock Synth.
Gain Offset
DEMUX
ADC
11
Sampled Data Flow
VME Board
FPGA
RAM
DSP
ADC
PM
trigger
LOGIC
S-Link
Controller FPGA
RAM
12
Software Design

• Measure pulse-shape by data from ADC
• Make decision about
• single or double hit
• kind of pulseform by cross-checking with pulse
  tables/function
• Calculate time and amplitude
• linear regression
• if
• single pulse get amplitude (comparators)
• substract values given by pulse
  tables/function,than get amplitude
• Pass through every 128th sampled event

13
Software Schematic
5,3 µs latency
Data odd Port0
1 DSP48E
4 DSP48E
Block RAM
exp. trigger
Pattern Detect Logic
FIR/ Moving Average Digital Filter
64k Circular Buffer
IBUF IDDR
Data even Port0
DSP48E
DSP48E
Segregate Double Hits/Halos
Gradient Max Value
DSP48E
CLB/DSP48E
Time information
Gradient Max Value
ADC trigger Port 0
Trigger Merger Logic
to ADC trigger system
ADC trigger Port 7
DSP48E
Amplitude information
Amplitude Fit
14
6U Size B
by Louis Lauser
USB/Ethernet PHY
Virtex5 XC5VSX95T
VME Drivers
VME CPLD
9MB QDRII IDT70P3517
Mini USB
USB/ PHY
Display
CLC 016
HOT Link
15 clock
VCO
3.3V GND
5.0V GND
3.3V GND
5.0V GND
3.3V GND
5.0V GND
3.3V GND
5.0V GND
LMK
VCO
VCO
VCO
VCO
JDS Uniphase
ADS 5463
ADS 5463
ADS 5463
ADS 5463
LMK
LMK
LMK
LMK
ADS 5463
ADS 5463
ADS 5463
ADS 5463
ADS 5463
ADS 5463
ADS 5463
ADS 5463
ADS 5463
ADS 5463
ADS 5463
ADS 5463
Analog Circuit
Analog Circuit
Analog Circuit
Analog Circuit
Analog Circuit
Analog Circuit
Analog Circuit
Analog Circuit
to ADCtrigger System
Display
15
Conclusion and Outlook

• We analysed different possibilities for a high
  resolution, high sampling rate readout electronic
  for the RPD
• We found a possible solution An eight channel
  ADC Board running in interleaved mode
• Serveral Test Boards are designed Clock, ADC EVB
  and VME
• A first Prototype before next Beamtime

16
Timetable
GHz Clk
0
n
m
n1
n2
Exp Clk
BOS
window
Trg
Input
time x ns
x
t