Register Binding for Clock Period Minimization

1
Register Binding for Clock Period Minimization

• Shih-Hsu Huang, Chun-Hua Cheng,
• Yow-Tyng Nieh, Wei-Chieh Yu

Department of Electronic Engineering Chung Yuan
Christian University, Taiwan
2
Outline

• Introduction
• Register Binding
• Optimal Clock Skew Scheduling
• Motivation
• The Proposed Approach
• MILP Approach
• Heuristic Approach
• Design Flow Issues
• Experimental Results
• Conclusions

3
Introduction (1/3)

• In logic synthesis stage, the clock skew has been
  widely utilized as a manageable resource for
  clock period minimization.
• Several graph-based algorithms have been proposed
  to solve the optimal clock skew scheduling
  problem in polynomial time complexity.
• However, no attention has been paid to the
  high-level synthesis of non-zero clock skew
  circuits.
• Conventional high-level synthesis assumes that
  the clock skew is zero.
• As a result, the circuit is never optimized for
  the utilization of clock skew.

4
Introduction (2/3)

• In fact, the register binding in high-level
  synthesis stage has a significant impact on the
  clocking constraints between registers.
• Different register binding solutions lead to
  different smallest feasible clock periods.
• Intuitively, if there is no register sharing
  (i.e., each register represents only one
  variable), the lower bound of the clock period
  can be achieved.
• However, no register sharing is impractical.
• This paper is the first attempt to the high-level
  synthesis of non-zero clock skew circuits.

5
Introduction (3/3)

• In this paper, we formally formulate the problem
  of register binding for clock period
  minimization. Given a constraint on the number of
  registers, our objective is to find a
  minimum-period register binding solution.
• Mixed Integer Linear Programming (MILP) Approach
• Heuristic Approach
• Experimental data show that, in most benchmark
  circuits, the lower bound of the clock period can
  be achieved without any extra overhead on the
  number of registers.

6
Outline

• Introduction
• Register Binding
• Optimal Clock Skew Scheduling
• Motivation
• The Proposed Approach
• MILP Approach
• Heuristic Approach
• Design Flow Issues
• Experimental Results
• Conclusions

7
Register Binding

• Two variables can share the same register, if
  they do not have overlapping lifetimes.
• The register binding problem is to assign the
  variables in the scheduled data flow graph (DFG)
  to the registers.
• Conventionally, the register binding problem
  assumes that the clock skew is zero.
• Conventionally, the objective is to minimize the
  number of registers.
• The widely used register binding algorithms
  include left edge approach and clique
  partitioning approach.

8
Left Edge Approach
R1 c,f R2 a,d,g R3 b,e
9
Outline

• Introduction
• Register Binding
• Optimal Clock Skew Scheduling
• Motivation
• The Proposed Approach
• MILP Approach
• Heuristic Approach
• Design Flow Issues
• Experimental Results
• Conclusions

10
Circuit Graph (1/2)

• Given a scheduled DFG and a register binding
  solution, we can use the circuit graph to model
  the final hardware implementation.
• Scheduled DFG
• Each control step corresponds to a clock cycle
• Each operation is implemented by a combinational
  logic (a functional unit)
• Each variable is stored in a register

11
Circuit Graph (2/2)
Delay of multiplier (12,16)
Delay of adder (3,4)
12
Constraint Graph
Hold
Setup
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Optimal Clock Skew Scheduling (1/2)

• Determine the smallest feasible clock period
• The clock period P is feasible, provided that the
  corresponding constraint graph has no negative
  cycle.
• A binary search strategy can be used to find the
  smallest feasible clock period in polynomial time
  complexity.
• Determine a clock skew schedule that works with
  the smallest feasible clock period
• This clock skew schedule can be found by
  solvingthe shortest path problem on the
  corresponding constraint graph.

14
Optimal Clock Skew Scheduling(2/2)
P 12
15
Outline

• Introduction
• Register Binding
• Optimal Clock Skew Scheduling
• Motivation
• The Proposed Approach
• MILP Approach
• Heuristic Approach
• Design Flow Issues
• Experimental Results
• Conclusions

16
Motivation

• Previous register binding algorithms do not take
  the utilization of clock skew into account.
• In fact, different register binding solutions
  impose different clocking constraints between
  registers. As a result, different register
  binding solutions lead to different smallest
  feasible clock periods.
• Intuitively, if there is no register sharing, the
  lower bound of the clock period can be achieved.
  However, since there is no register sharing, this
  register binding solution uses too many registers
  and thus it is impractical.

17
No Register Sharing
R1 a
7 Registers
P 12
R2 b , R3 c, R4 d
R5 e , R6 f, R7 g
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Left Edge Register Binding
P 16
3 Registers
R1 c,f R2 a,d,g R3 b,e
19
Our Register Binding
P 12
3 Registers
R1 c,f R2 a,d R3 b,e,g
20
Outline

• Introduction
• Register Binding
• Optimal Clock Skew Scheduling
• Motivation
• The Proposed Approach
• MILP Approach
• Heuristic Approach
• Design Flow Issues
• Experimental Results
• Conclusions

21
The Proposed Approach

• Given a scheduled DFG and a constraint on the
  number of registers, our objective is to minimize
  the clock period via the application of
  simultaneous register binding and optimal clock
  skew scheduling.
• We use mixed integer linear programming (MILP) to
  formally formulate the problem.
• Our MILP formulation guarantees obtaining the
  optimal solution.
• We also propose a heuristic algorithm to obtain a
  near-optimal solution.
• The time complexity is O(m?n?TOCSS), where m is
  the number of variables, n is the number of
  registers, and TOCSS is the time complexity of
  optimal clock skew scheduling used.

22
Outline

• Introduction
• Register Binding
• Optimal Clock Skew Scheduling
• Motivation
• The Proposed Approach
• MILP Approach
• Heuristic Approach
• Design Flow Issues
• Experimental Results
• Conclusions

23
MILP Approach

• Our MILP formulation guarantees obtaining the
  optimal solution.
• The objective is to minimize the clock period P,
  subject to
• Resource constraint
• Lifetime constraint
• Register assignment constraint
• Setup constraint
• Hold constraint

24
Resource Constraint
Each variable must be assigned to one register.
Given 3 registers
xa,1xa,2xa,31 xb,1xb,2xb,31 xc,1xc,2xc,3
1 xd,1xd,2xd,31 xe,1xe,2xe,31
xf,1xf,2xf,3 1 xg,1xg,2xg,31
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Lifetime Constraint
If two variables have overlapping lifetimes,they
cannot share the same register.
xa,1xb,1xc,1 1 xa,2xb,2xc,2
1 xa,3xb,3xc,3 1 xc,1xd,1xe,1
1 xc,2xd,2xe,2 1 xc,3xd,3xe,3 1
xf,1xg,1 1 xf,2xg,2 1 xf,3xg,3 1
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Register Assignment Constraint
If variable u is assigned to register Ri, then
the valueof Tu must be exactly the same as Ti.
On the other hand, if variable u is not assigned
to register Ri, then there is no constraint on
the clock skew between Tu and Ti.
Ta-T1(1-xa,1)s T1-Ta(1-xa,1)s
Ta-T2(1-xa,2)s T2-Ta(1-xa,2)s
Ta-T3(1-xa,3)s T3-Ta(1-xa,3)s .
. . . . .

Constant s ? ?
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Setup Constraint
For the input variable and the output variable of
thesame operation, the maximum delay must
satisfythe setup constraint.
Thost Ta P 16 Thost Tb P 4 Thost
Tc P 4 Thost Td P 16 Ta Te P
4 Tb Te P 4 Tc Tg P 4 Td Tf P
4 Te Tg P 4 Tf Thost P 16 Tg
Thost P 16
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Hold Constraint
For the input variable and the output variableof
the same operation, the minimum delay
mustsatisfy the hold constraint.
Ta Thost 12 Tb Thost 3 Tc Thost
3 Td Thost 12 Te Ta 3 Te Tb 3 Tg
Tc 3 Tf Td 3 Tg Te 3 Thost Tf
12 Thost Tg 12
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The Solution of MILP Formulation
xc,1 xf,1 xa,2 xd,2 xb,3 xe,3 xg,3
1, Thost 0, T1 Tc Tf -4, T2 Ta Td
4, T3 Tb Te Tg -4.
P 12
R1 c,f R2 a,d R3 b,e,g
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Outline

• Introduction
• Register Binding
• Optimal Clock Skew Scheduling
• Motivation
• The Proposed Approach
• MILP Approach
• Heuristic Approach
• Design Flow Issues
• Experimental Results
• Conclusions

31
Heuristic Approach

• Our heuristic algorithm is an iteration process
  of assigning variables to registers. The
  iteration process repeats until all the variables
  are assigned to registers.
• Initially, each variable is unassigned. The
  priorities of choosing an unassigned variable
• If an unassigned variable has only one register
  that can be assigned (due to the lifetime
  constraint), this variable has the highest
  priority.
• For two unassigned variables that have more than
  one register can be assigned, the variable that
  has a smaller width of possible clock arrival
  time has a higher priority.

32
The Width of Possible Clock Arrival Time
The earliest possible clock arrival time Eu
-1dist(u,host) The latest possible clock
arrival time Lu 1dist(u,host)
The width of possible clock arrival time Wu
Lu - Eu
P 12
Ea 4, La 12
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An Example (1/12)
Our heuristic algorithm starts from the result of
left edge binding R1 c,f R2 a,d,g R3
b,e -------------------------------------- R1
? Wf lt Wc ( 0 lt 11 ) R2 ? Wd lt Wa Wg ( 0 lt 8
8 ) R3 ? We lt Wb ( 8 lt 10 ) -------------------
-------------------
P 12
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An Example (2/12)
R1 f R2 d R3 e
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An Example (3/12)
Due to the lifetime constraint, we assign
variable c to register R1. R1 c,f R2 d
R3 e --------------------------------------
P 12
36
An Example (4/12)
Variables a, b, and g have more than one register
that can be assigned. Wa Wg lt Wb ( 8 8 lt 10
) -------------------------------------- We
choose variable a
P 12
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An Example (5/12)
If variable a is assigned to register R2, 1.
The smallest feasible clock period is still
12. 2. Total possible clock arrival time
width becomes 26. Wb Wg W1 W2 W3
26 --------------------------------------
P 12
38
An Example (6/12)
If variable a is assigned to register R3, 1.
The smallest feasible clock period is still
12. 2. Total possible clock arrival time
width becomes 2. Wb Wg W1 W2 W3
2 --------------------------------------
P 12
39
An Example (7/12)
Variable a is assigned to register
R2. -------------------------------------- R1
c,f R2 a,d R3 e
P 12
40
An Example (8/12)
Due to the lifetime constraints Variable b only
can be assigned to registers R3. R1 c,f R2
a,d R3 b,e
P 12
41
An Example (9/12)
Variables g can be assigned to register R2 or
register R3.
P 12
42
An Example (10/12)
If variable g is assigned to register R2, the
smallest feasible clock period becomes 16.
P 16
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An Example (11/12)
If variable g is assigned to register R3, the
smallest feasible clock period is still 12.
P 12
44
An Example (12/12)
We assign variable g to register R3. R1
c,f R2 a,d R3 b,e,g
P 12
45
Outline

• Introduction
• Register Binding
• Optimal Clock Skew Scheduling
• Motivation
• The Proposed Approach
• MILP Approach
• Heuristic Approach
• Design Flow Issues
• Experimental Results
• Conclusions

46
Design Flow Issues (1/2)

• Our approach has no limitation on the given
  scheduled DFG.
• Even if the data path contains chained operations
  and multi-cycle operations, the optimal clock
  skew scheduling is still applicable.
• Our approach is applicable to the control path
  (i.e., our approach is not limited to the data
  path).
• Some papers ever studied the delay estimation of
  control path.
• By estimating the delay of control path, the
  optimal clock skew scheduling can be applied to
  both the data path and the control path.

47
Design Flow Issues (2/2)

• The design closure (design convergence) can be
  achieved.
• To tolerate the uncertainty, the clock arrival
  time of each register can be modeled as a range
  instead of a single value.
• Even if the clock arrival time is modeled as a
  range, the optimal clock skew scheduling is still
  applicable.

48
Outline

• Introduction
• Register Binding
• Optimal Clock Skew Scheduling
• Motivation
• The Proposed Approach
• MILP Approach
• Heuristic Approach
• Design Flow Issues
• Experimental Results
• Conclusions

49
Experimental Method

• Implementation of our approach
• We use Extended Lingo Release 8.0 asthe MILP
  solver.
• We also use C programming language to implement
  the heuristic algorithm.
• Benchmark Circuits
• Popular DSP applications and MediaBench suite
• We use the slack driven scheduling algorithm to
  derive the scheduled DFG
• All the functional units (i.e., all the
  operations)are implemented by using Synopsys
  DesignWare.
• 8-bit designs
• Artisan UMC 0.18µm cell library

50
Analysis to Circuit BF
The minimum number of registers 6 The lower
bound of the clock period 4.03
51
Analysis to Circuit EWF
The minimum number of registers 11 The lower
bound of the clock period 4.03
52
Analysis to Circuit IDCT1
The minimum number of registers 21 The lower
bound of the clock period 11.05
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Analysis to Circuit Sha1
The minimum number of registers 100 The lower
bound of the clock period 4.03
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Analysis to Circuit Motion
The minimum number of registers 111 The lower
bound of the clock period 11.05
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Outline

• Introduction
• Register Binding
• Optimal Clock Skew Scheduling
• Motivation
• The Proposed Approach
• MILP Approach
• Heuristic Approach
• Design Flow Issues
• Experimental Results
• Conclusions

56
Conclusions

• This paper is the first attempt to the high-level
  synthesis of non-zero clock skew circuits.
• We show that the register binding has a
  significant impact on the utilization of clock
  skew. Based on that observation, we propose an
  approach to obtain the minimum-period register
  binding solution.
• In most benchmark circuits, the lower bound of
  the clock period can be achieved without any
  extra overhead on the number of registers.
• The clock skew can also be utilized to improve
  the circuit reliability. This extension of our
  approach is straightforward.

57
Thank you