M' F' Chiang, Z' Ghassemlooy, Wai Pang Ng,

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All-optical Packet Switched Router With Multiple
Pulse Position Routing Tables
M. F. Chiang, Z. Ghassemlooy, Wai Pang Ng, and
H. Le Minh Optical Communication Research
Group Northumbria University, United
Kingdom http//soe.unn.ac.uk/ncrlab/
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Contents

• Introduction
• PPM Routing Table (PPRT) Multiple PPRTs
• Address Correlation with Multiple PPRTs
• Proposed Node Architecture
• Simulation Results
• Conclusions

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Introduction

• There is a growing demand for all optical
  switches and router at very high speed, to avoid
  the bottleneck imposed by the electronic
  switches.
• The development of ultra high-speed all-optical
  switches logic gates (such as AND, OR and XOR)
  with operating data rates above 40 Gbit/s have
  become the key enabling technology for realising
  all-optical routers.

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Introduction Optical networks

Optical Packet
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Introduction- Research Aim

• Packet processing in a large dimension network
  (routing table with hundreds or thousands of
  entries) results in throughput latency. Therefore
  by converting packet header and the routing table
  from a binary RZ into a pulse position modulation
  (PPM) format. The size of the PPM routing table
  is significantly reduced.
• Furthermore, by employing multiple PPRTs, only a
  subset of the header address are converted into a
  PPM format, thus resulting in a reduced length of
  PPRT entries thus resulting in a faster packet
  processing.

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PPM Conversion




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Routing Table
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Address Correlation with Multiple PPRTs
11100 28d
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Multiple PPRTs
Check MSBs a4 a3 (X2)
a4 a3 10
a4 a3 01
a4 a3 00
a4 a3 11
a2 a1 a0
EA (24 31)
EB (16 23)
EC (8 15)
ED (0 7)
E1A
E2A
E3A
E1B
E2B
E3B
E1C
E2C
E3C
E1D
E2D
E3D
E1
E2
E3
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Node architecture
All-optical Switch
Port 1
OSW1
Port 2
OSW2


Port M
OSWM
Header Extraction
PPM Add. Conversion
CP 1
CP 2
Multiple PPRT
CP M
OSWC

Entry 1
1
Clock Extraction
Entry 2
OSWC
2
Synchronisation



Entry M
OSWC
M
Group A
SW3
Group B
Unicast transmission
SW4
Multiple PPRT Generator
Group C
SW3
Group D
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Node architecture
All-optical Switch
Port 1
OSW1
Port 2
OSW2


Port M
OSWM
Header Extraction
PPM Add. Conversion
CP 1
CP 2
Multiple PPRT
CP M
OSWC

Entry 1
1
Clock Extraction
Entry 2
OSWC
2
Synchronisation



Entry M
OSWC
M
Group A
SW3
Group B
Multicast transmission
SW4
Multiple PPRT Generator
Group C
SW3
Group D
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Node architecture
All-optical Switch
Port 1
OSW1
Port 2
OSW2


Port M
OSWM
Header Extraction
PPM Add. Conversion
CP 1
CP 2
Multiple PPRT
CP M
OSWC

Entry 1
1
Clock Extraction
Entry 2
OSWC
2
Synchronisation



Entry M
OSWC
M
Group A
SW3
Group B
Broadcast transmission
SW4
Multiple PPRT Generator
Group C
SW3
Group D
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Simulation Results-Simulation Parameters
Simulation Tool Virtual Photonic Inc. (VPI)
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Simulation Results-Time Waveforms
(a) input packet
(b) extracted clock signals
(c) matched signals at AND1
(d) switched packets at routers output 1
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Simulation Results-Time Waveforms
(e) matched signals at AND2
(f) switched packets at routers output 2
(g) matched signals at AND3
(h) switched packets at routers output 3
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Conclusions

• In this paper, the principle of the new multiple
  PPRTs and the node architecture were proposed.
• It was shown that by using multiple PPRTs, the
  number and the length of entries are
  significantly further reduced compared with
  existing RTs and PPRTs, respectively.
• The proposed router offers a faster processing
  time especially for packets with long address
  bits. and is capable of operating in the unicast,
  multicast and broadcast transmission modes.

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Acknowledgements

• Special Thanks for
• Prof. Fary Ghassemlooy
• Dr. Wai Pang Ng
• Mr. Hoa Le Minh
• All colleagues in NCRL
• Your Attention

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• Thank You !

Question, please ?