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3. Background ... PlayStation 3. Processor Speed OK, limite

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3. Background ... PlayStation 3. Processor Speed OK, limited to 100T Ethernet or USB2 interface ... Decimate by 3. Output data rate now 63/3 = 21Msps. But, ... – PowerPoint PPT presentation

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Title: 3. Background ... PlayStation 3. Processor Speed OK, limite


1
Fully Digital HF Radios
  • Phil Harman VK6APH

Dayton Hamvention 17th May 2008
2
Overview
  • Software Defined Radios are now providing
    performance equal to the best Analogue designs
  • Theres is a new trend in HF SDR radios that
    eliminates most of the Analogue components.
  • In effect the antenna is connected directly to an
    Analogue to Digital Converter (ADC).
  • So how does this next generation of SDRs work?
  • How well do they work?

3
Background
  • Most current SDRs use PC sound cards or audio
    ADCs to provide analogue to digital conversion

LPF
I
BPF

0 192KHz
90
LPF
Q
4
SDR
5
Performance
  • Bandscope width restricted to sound card sampling
    rate e.g. max of 192KHz
  • Image response
  • e.g. Receiver tuned to 14.100kHz, with 10kHz IF,
    then image will be at 14.080kHz

6
Performance
  • Image rejection limited by analogue components
  • Rejection Phase(deg) Amplitude(dB)
  • 40dB 1.0 0.1
  • 60dB 0.1 0.01
  • 80dB 0.01 0.001
  • 100dB 0.001 0.0001
  • This accuracy must hold over each ham band and
    300Hz-3kHz, with temperature, component aging,
    vibration, voltage fluctuations etc

7
Performance
  • We can compensate digitally for consistent phase
    and amplitude errors
  • Automatically and manually

8
I Q Error Correction
  • Can provide gt90dB of image rejection at a single
    frequency either manually or automatically
  • But - image rejection will drop at band edges
  • So - apply the correction at multiple frequencies

9
I Q Error Correction
Switch on
After one day
  • Rocky software (Alex, VE3NEA) learns how to
    correct I and Q using off-air signals

10
I Q Error Correction
  • Not the full solution since
  • We need enough, strong signals, for the
    calibration to work
  • The calibration will change with SWR, temperature
    etc
  • Needs doing on each band
  • Its time consuming
  • This doesnt mean it not a solvable problem
    some really smart people are working on it!

11
Fully Digital Approach
Data
Digital Signal Processor
A
D
Audio
D
A
12
Fully Digital Approach
  • ADC requirements
  • Must sample gt twice max receiver frequency
  • For 0 30MHz sample at gt60MHz
  • Need gt120dB of dynamic range
  • At 6.02dB per bit need 20 bits

13
Fully Digital Approach
  • ADC how much can we afford?
  • For 100
  • Linear Technology - LT2208
  • Sample rate 130Msps
  • Input bandwidth 700MHz
  • Bits 16
  • Wide band noise floor - 78dBFS

14
Fully Digital Approach
  • DSP interface

Data
Digital Signal Processor
A
D
Audio
D
A
Data Rate
15
Fully Digital Approach
  • Speed requirements
  • 16 bit samples _at_ 63Msps
  • 1000 Mbps i.e. 1Gbps
  • Options
  • Firewire 400Mbps
  • USB2 480Mbps
  • Firewire800 800Mbps
  • USB3 4.8Gbps (Q2 2008)
  • Ethernet 1 10Gbps
  • PCIe 64Gbps
  • In practice Firewire is faster than USB2 due to
    Peer-to-Peer architecture

16
Fully Digital Approach
  • DSP requirements
  • PC Quad Core PC
  • Processor speed OK, limitation is getting data in
    and out of the processors' main address space
  • PlayStation 3
  • Processor Speed OK, limited to 100T Ethernet or
    USB2 interface
  • Expect to process 46MHz of spectrum

17
Fully Digital Approach
  • Digital to Analogue Conversion (DAC)
  • For Audio output need 16 bits at 8ksps
  • 128ksps
  • Modern sound cards/chips do gt 4Mbps

18
Fully Digital Approach
  • Reality Check!
  • ADC not meet our needs
  • USB2 or Firewire will give 240Mbps to PC
  • Enough for a 60MHz wide bandscope or 6
    simultaneous receivers each 300kHz wide
  • So we compromise!

19
Fully Digital Approach
  • With Analogue radios we dont process 0 - 30MHz
    simultaneously
  • We process a single frequency and a narrow
    bandwidth e.g. 3kHz
  • Can we apply the same process to a fully digital
    radio?
  • Yes! We use Digital Down Conversion which is
    based on Decimation.

20
Fully Digital Approach
  • Decimation

Decimator (divide by n)
16 bit samples _at_ 63/n Msps
A
D
16 bit samples _at_ 63Msps
21
Fully Digital Approach
ADC Output
22
Fully Digital Approach
ADC Output Decimate by 3
23
Fully Digital Approach
  • Decimate by 3
  • Output data rate now 63/3 21Msps
  • But, maximum input frequency now lt10.5MHz
  • What if we use superhet techniques?

24
Digital Down Conversion
25
HPSDR Mercury DDC Receiver
  • LT2208 ADC sampling at 125MHz
  • ADC output 0 60MHz
  • Decimate by 640
  • Output 125MHz/640 195ksps
  • 24 bit samples
  • 24 x 195,000 4.68Mbps
  • Bandscope now 195kHz wide

26
HPSDR Mercury DDC Receiver
  • By decimation we have eased the load on the PC
    but increased the complexity of the DDC
  • But there is an additional advantage of
    decimation!
  • Every time we decimate by 2 we increase the
    output SNR by 3dB

27
HPSDR Mercury DDC Receiver
By decimating from 60MHz to 3kHz we improve the
SNR from 78dB to 121dB
28
Performance
  • Standard way of measuring receiver performance
  • 3rd Order Intermodulation Products
  • Inject two equal amplitude signals in the antenna
    socket
  • Any non-linear stages will create 2nd harmonics
  • These mix with the fundamentals to produce 3rd
    order IP

29
Performance
  • 3rd Order IP
  • Inject two equal amplitude signals

f1 f2
dB
0 2 4 5 6 8 10
12 14 16 18
Input MHz
30
Performance
  • 3rd Order IP
  • Inject two equal amplitude signals
  • Any non linear stages will create harmonics

f1 f2
dB
2f1
2f2
3f2
3f1
0 2 4 5 6 8 10
12 14 16 18
Input MHz
31
Performance
  • 3rd Order Intermodulation Products

f1 f2
dB
2f1-f2
2f2-f1
0 2 4 5 6 7 8 10
12 14 16 18
Input MHz
32
Performance
  • Graph of IP3 for Analogue Receiver

3rd order intercept point
Saturation
Output dB
Fundamental (Slope 1)
3rd Order IMD (Slope 3)
Input dB
33
Performance
  • Graph of IMD for ADC based Receiver

Intersection has no practical significance
Saturation
Output dB
Fundamental (Slope 1)
IMD Products (Slope 1)
Input dB
34
Performance
  • Graph of IP3 point verses input level

Analogue Receiver
Saturation
IP3 dB
Digital Receiver
Input dB
35
Performance
  • What causes IMD to vary with input level?
  • Fewer bits are used at low input levels
  • Non ideal ADC performance

36
Performance
  • Ideal ADC

Digital Output
Analogue Input
37
Performance
Performance
  • Real-world ADC

Analogue Input
Digital Output
38
Performance
Performance
  • Real-world ADC

Analogue Input
Digital Output
39
Performance
40
Performance
41
Performance
  • Sources of dither
  • In band signals and noise
  • Out of band signals and noise
  • Internal pseudorandom noise
  • Added external signal
  • As long as all the external signals dont add..
    Then big signals are your friend.

42
Fully Digital HF Radios
  • Summary
  • Fully digital receivers perform differently to
    analogue ones
  • IP3 measurements are not meaningful.
  • Large signals can improve the performance of
    digital receivers
  • In practice
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