Electrical and Computer Engineering Department

1
Low-Cost Parameterizable Bloom Filter
Implementation for FPGAs

• Electrical and Computer Engineering Department
• 18-740 Research Project
• Ryan Sakauye David Lewis
• rsakauye_at_andrew.cmu.edu delewis_at_andrew.cmu.edu

2
Bloom Filter

• A memory efficient data structure for testing set
  membership
• Many applications for computer architecture
• Transactional Memory
• m-bit vector with k hash functions
• Never returns a false negative may however
  return false positive
• False positive rate described by
• where n is the number of elements

A bloom filter with three hash functions
containing x,y,z. The element w is queried and
not contained.
For optimal m and n, the optimal number of hash
functions is
3
Our design and motivation

• Conventional Bloom filter did not fit on FPGA!
• Logic to work with big enough bit vector too
  large for FPGA
• Partition the original filter and hash functions
  into sub-filters with unique hash functions
• Allows the same number of insertions as the
  original filter
• False positive rate of each sub- filter fixed as

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Filter generation

• Each inserted item divided into fixed-size chunks
  (flits) for hashing
• XOR-based block hashing for simplicity
• Enable lines in filter generation to allow
  parameterizable number of used hash functions

5
Datapath

• Synchronous register file allowed us to use block
  RAM, which made our design even smaller

6
Experimental Setup

• Several test cases to validate correctness of
  design
• Confirmed addition of sequential and random
  integers resulted in no false-negatives when
  queried
• Additional test cases to measure false-positive
  rate of filter
• Populated filter with sequential and random
  integers, then queried elements not in the set to
  count number of false positives
• Test case generation and output parsing was done
  in C
• Communicated with design over a serial connection
  with a baud rate of 115200 using Hyperterminal
• Synthesis was done using Xilinx ISE 11 for a
  Xilinx Spartan3 FPGA

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Utilization sensitivity to parameters

• Using a small FPGA, so many cases have above 100
  utilization
• Most sensitive to filter size (m)
• With good block hashing algorithm, flit size can
  be small
• Red lines show 100 utilization on Spartan3 board
• If design fits in
• BRAM, regfile
• size has small
• impact on
• utilization

Didnt fit in BRAM
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Conclusion and Future Work

• Conclusion
• Our design worked correctly, though the false
  positive was much larger than the theoretical
  rate given an ideal set of hash functions

• Future Work
• Try our design with better hash functions
• Possible Issue Keeping the logic of the hash
  small enough to continue to fit on FPGA
• Use the scheme pictured, with the same hash
  functions for each sub-filter
• Theoretical capacity smaller than equivalent
  sized large bloom filter, but might do better
  through intelligent filter selection
• Larger datapath (need population count modules)
• Joining filters becomes complicated
• Potentially more complicated control logic