Layout and simulation of low power fulladder cells

1
Layout and simulation of low power full-adder
cells

• Peter Mettler

2
Layout and simulation of low power full-adder
cells

• Introduction
• Pre layout simulation of primitive arithmetic
  cells
• Layout and post layout simulation

3
Introduction

• Power consumption
• Reduction of power consumption
• MOS technologies

4
Power consumption

• Static power (leakage currents)
• Switching power
• Short-circuit power

5
Static power

• PDC VDD/2.ID.(Vinlow)ID.(Vinhigh)
• Only leakage currents for CMOS (PDC 0)

6
Switching power

• Caused by charge up and down ofcapacitor Cload
• Pavg?T.Cload.VDD2.f?T node transition factor
  (1 for inverter)

7
Short-circuit power

• Caused by turning on both transistors due to slow
  raise/fall of input signal

8
Reduction of power cunsumption

• How to measure performance?
• Voltage scaling
• Reducing switching activity
• Reduction of operating frequency
• Reduction of short circuit power

9
How to measure performance?

• Quality and performance of a circuit depends on
  power and delay
• Power-Delay-Product Pavg.?max
• Energie mainly dissipated as heat?try to
  minimize Power-Delay-Product

10
Voltage scaling

• Pavg Cload.VDD2.f depends most on the voltage
  VDD ? reduce VDD
• Reduction of power
• Increase of delay

11
Reducing switching activity

• Glitches are producing a lot of wasted power?
  reduce glitches (decreases ?T)

12
Reduction of operating frequency

• less charge up/down of output capacitance
• less performance
• Only applicable if speed is not critical

13
Reduction of short circuit power

• Short circuit power is caused by slow rise and
  fall times of input signal? shorten rise and
  fall times of input signal if possible

14
MOS technologies

• Complementary MOS (CMOS)
• Complementary Pass transistor Logic (CPL)
• Dual Pass transistor Logic (DPL)

15
Complementary MOS (CMOS)

• nMOS and pMOS for logical function
• Regular structure
• Well known for low power circuits

16
Complementary Pass transtistor Logic (CPL)

• Uses nMOS Pass transistors for logical function
• pMOS to restore full swing at output
• Complementary input signals required

17
Dual Pass transistor Logic (DPL)

• Uses nMOS/pMOS Pass transistors for logical
  function
• Complementary input signals required

18
Pre layout simulation of primitive arithmetic
cells

• Full adder
• 4-2 compressor
• 5-2 compressor

19
Full adder

• Schematic
• Simulation
• Result

20
Schematic
21
CMOS-design
22
CPL-design
23
DPL-design
24
Simulation
25
Result 0.35um
26
Result 0.18um
27
4-2 compressor

• Schematic
• Simulation
• Result

28
Schematic
29
Simulation
30
Result
31
5-2 compressor

• Schematic
• Simulation
• Result

32
Schematic
33
Simulation
34
Result
35
Result
36
Layout and post layout simulation (CLA)

• Schematic
• Pre layout simulation
• Layout
• Post layout simulation

37
Schematic
38
Pre layout simulation

• Ensure right function of the schematic
• Ensure full swing of all outputs
• Find first signs for problems with post layout
  simulation

39
Layout
40
Post layout simulation

• More accurate than pre layout simulation
• Closer to reality

41
Thanks for your attention

• Any questions?