DOM HUB

1
DOM HUB

• Design Proposal
• K.-H. Sulanke
• DESY Zeuthen

2
Contents

• Introduction
• DOM HUB
• DOR - DOM Readout board
• Optimized cable interface
• Test setup
• Conclusions

3
Introduction

• idea full string control out of one box
• industry PC for DOM HUB
• single slot CPU
• 80 V power supply (?)
• 8 DOR (DOM Readout) boards
• clock distribution / slow control board

4
Industry PC
ICECUBE Meeting, Berkeley March 2002
12/31/2009
K.-H. Sulanke, DESY Zeuthen
4
5
Single Slot CPU

• off the shelve, from 100MHz P3...2GHz P4
  available
• functional equivalent to a desktop mainboard

6
Backplane, 2 CPU-, 12 PCI slots
7
DOR board
8
Analog Region
9
DOMCOM / TB Cable Interface

• Problem need of board area, 4 power resistors, 2
  transformers
• 20V (!!!) DC loss at cable terminating resistors
• additional power 0.13 W / DOM, 624 W / 4800 DOMs

10
DOR Cable Interface, less is more ?

• low power cable termination resistor
• 1.2 V overall DC loss now (2 DOMs _at_ 50mA)
• one transformer only

11
DOR Cable Interface, Tested Schematic

• Communication ADC, /- 1 digit noise only
• long term fast communication tests with modified
  DOMCOMs
• more stable against electromagnetic distortions
• time calibration tests next (2 DOMs connected)

12
Cable Termination, Two DOMs Per Line

• classic style - termination at both ends, easy
  to implement

13
Proposed DOM Cable Connection

• tested cable arrangement

glass sphere
14
Test Setup
Test PC DOS BorlandC

• 3 modified DOMCOM boards used
• DOR sends addressed random length packets
  (1...2048 bytes) of random data, transfer speed
  is 1Mbit/s
• DOM_1 or DOM_2 are receiving packets and
  sending them back 12 µs after arrival of the last
  byte
• packets are verified at the DOR PC before
  sending the next packet

17m cable
DOR board
lower DOM board
upper DOM board
2.6 km cable
15
DOM Board
cable adapter
components removed
address jumper
DC / DC converter
ICECUBE Meeting, Stockholm June 2002
12/31/2009
K.-H. Sulanke, DESY Zeuthen
15
16
Signals, 130 ? Termination at lower DOM
1V
17
Reflections, 130 ? Termination at lower DOM
1V
18
Reflections, 240 ? Termination at both DOMs
1V
19
Data Traffic, Surface Side

• transfer test is loading the cable almost all the
  time
• quiet gaps due to data checking and the OS

20
DOM - Turnaround Cycle

• packets are sent as one consecutive datastream
  always
• DOM starts sending after a gap of 12 µs (could
  be less)

21
DOM Control Statemachine
22
Data Traffic, DOM_1/2 Select Signals

• two DOMs in slave mode, reflecting packets
  (1Byte..2KB)
• random addressing, random data, random packet
  length
• a high pulse represents the receiving and the
  sending cycle

23
Status Next Steps

• simplified cable interface works well
• cable termination easy to achieve
• fast communication with 2 DOMs error free (20 GB)
• time calibration tests next
• detailed DOR schematic soon
• DOR prototype in October ?
• still to clarify 80V power supply
• still to design DOM HUB slow control board