LucasLehmer Primality Tester Presentation 6 March 1st 2006

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Lucas-Lehmer Primality TesterPresentation
6March 1st 2006

• Team W-4
• Nathan Stohs W4-1
• Brian Johnson W4-2
• Joe Hurley W4-3
• Marques Johnson W4-4
• Design Manager
• Prateek Goenka

Overall Objective Modular Arithmetic unit with a
creative use
This is my presentation, there are others like it
but this one is mine
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Status

• Finished
• Project Chosen
• C simulations
• Behavioral Verilog
• Structural Verilog
• Revised Floor Plan
• Schematics ( 98)
• In Progress
• Top Level Simulations
• Layout
• Layout Simulations
• To Do
• Continue Layout
• Layout Simulations
• Pathmill Simulation on Top Level

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Design Decisions

• Optimization
• Got rid of universal Shifter
• Implemented Shifter_Left Shifter_Right
• Stressed special cases over universal parts
• Cut out 4,000 transistors

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Transistor Counts (Old)
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Transistor Counts (New)
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Power Consumption
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Shift_Left
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(No Transcript)
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(No Transcript)
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Shift_Right
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(No Transcript)
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(No Transcript)
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Mod_P
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(No Transcript)
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(No Transcript)
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Partial Product
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(No Transcript)
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(No Transcript)
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Pathmill Results

• Shift_Left .610 ns
• Shift_Right .610 ns
• Mod_P .610 ns
• Mod_Add 8.993 ns
• Partial_Products 5.135 ns

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Initial Layout
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More Layout
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Block Area Estimates (Old)
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Block Area Estimates (Updated)
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Updated Floorplan
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Whats Next

• Continue Layout
• Pathmill Simulations for Top Level
• Simulate Layout

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Questions?