Synthesis of Predictable NoCBased Interconnect Architectures for CMPs

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Synthesis of Predictable NoC-Based Interconnect
Architectures for CMPs

• Presented by
• Omar Al Ibrahim

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• Murali, S.   Atienza, D.   Meloni, P.   Carta,
  S.   Benini, L.   De Micheli, G.   Raffo, L.,
  Synthesis of Predictable NoC-Based Interconnect
  Architectures for CMPs, IEEE Transactions on
  VLSI, Vol 15, No. 8, Aug 2007

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Network on Chip (NoC)

• Emerging paradigm in VLSI
• Benefits
• Performance
• Better structure
• Modularity
• System types
• Application-Specific Systems on Chip (ASSoCs)
• Chip Multiprocessors (CMPs)

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NoC Design Challenges for CMPs

• Traffic pattern characterization
• Link bandwidth utilization
• Performance guarantees

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Previous Work

• NoC architectures
• Application traffic analysis
• Mapping, routing, resource reservation for
  predictable NoCs
• Topology exploration of NoCs

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NoC Synthesis Design Flow
Obtain NoC topology, routing, core speed,
data-width, NoC flit-width
Vary NoC frequency in user defined range
NoC floorplan
Determine number of physical channels on each
link and static assignment of flow
Determine switch sizes, link lengths
Do switches meet target frequency ?
Store the current configuration and power
consumption
no
Switch library
Timing libraries
yes
Do links meet target frequency ?
no
Determine NoC power consumption
Wire library
yes
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Problem Formulation

• P(V,L) NoC topology graph
• vi ? V core
• lij (vi, vj) ? L link between vertices
  vi and vj
• CH(i,j) physical channels instantiated
  for link lij

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Problem Formulation (cont.)

• d(k) where k0,1,,VxV flow commodity
• source(dk) source commodity
• dest(dk) destination of flow
• R dk ? L , ?k routing function
• rate(dk) rate of traffic injection

A single link with 2 physical channels
l(0,1)
V0
V1
l(1,0)
l(3,1)
l(0,2)
l(2,0)
l(1,3)
l(2,3)
V2
V3
l(3,2)
l(5,3)
l(2,4)
l(4,2)
l(5,3)
l(4,5)
V4
V5
l(5,4)
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Problem Statement

• To determine the number of channels CH(i,j)
  required for each link l(i,j) and a static
  mapping of each commodity d(k) onto a single
  channel ch? CH(i,j) of each link l(i,j)? L(k).

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Synthesis Algorithm

• NoC Link Sizing
• Build the Link Loading Graph(LLG)
• Build the Vertex Conflict Graph (VCG)
• Create m max-cut partitions of VCG
• Build Partition Loading Graph (PLG)
• Timing Feasibility Check

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Link Loading Graph (LLG)

• LLG i,j (LV, LL) is a bipartite graph
• LV 2 x V
• ll(x,y) (lv(x), lv(y)) ?x?0,, V-1,
  ?y?0,,2xV-1 if ?k s.t source(dk) lv(x) and
  dest(dk) lv(y-V) and l(i,j)?L(k)
• The weight of the edge is rate(dk)

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Vertex Conflict Graph (VCG)

• VCG(i,j) (VV, VL), VV V
• vl(i,j) (vvi, vvj) if degree(lvi)degree(lvj) gt0
• The weight of the edge is the max. weight
  bipartite matching of modified LLG
• The partitioning is such that the sum of the edge
  weights cut across is max and total number of
  vertices in each partition is the same

Partition 2
vv0
800
vv1
400
400
400
400
400
vv4
vv2
400
vv3
400
400
vv5
Partition 1
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Partition Loading Graph (PLG)
lv0
lv6
lv0
lv6
400
lv1
lv7
lv1
lv7
400
400
lv8
lv8
lv2
lv2
lv3
lv9
400
lv3
lv9
lv4
lv10
lv4
lv10
lv5
lv5
lv11
lv11
PLG2
PLG1
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Experimental Results

• Experiments on a Mesh Topology
• Effect of Core Injection Rates
• Effect of Different NoC Sizes
• Effect of Link Length
• Application to Torus Topology

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Experiments on a Mesh Topology
NoC Power Consumption(in mW)
v0
v1
v2
v3
v4
500
v5
v6
v7
v8
v9
400
v10
v11
v12
v13
v14
300
200
v19
v16
v17
v15
v18
100
v20
v21
v23
v22
v24
0
400
500
600
700
800
900
5 x 5 Mesh Topology
NoC Operating Frequency (MHz)
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Effect of Core Injection Rates
NoC Power Consumption (in mW)
1200
Reference
Proposed
1000
800
600
400
200
0
100
200
300
400
500
Core Operating Frequency (in MHz)
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Effect of Different NoC Sizes
Normalized NoC Power Consumption
1
0.8
0.6
0.4
0.2
0
6x6
7x7
8x8
9x9
10x10
5x5
4x4
Mesh Sizes
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Effect of Link Length
NoC Power Consumption (in mW)
400
Switch power
Link power
300
200
100
0
1
2
3
4
Link Length (in mm)
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Application to Torus Topology
NoC Power Consumption (in mW)
400
300
200
100
0
Routing 2 (with wrap-around)
Routing 1 (w/o wraparound)
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Conclusion

• Synthesis method of NoC interconnect for CMPs
• Future directions Explore different NoC
  topologies and routing functions

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Thank You