COMP 4300 Computer Architecture Datapath

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COMP 4300 Computer Architecture Datapath
Dr. Xiao Qin Auburn Universityhttp//www.eng.aubu
rn.edu/xqin xqin_at_auburn.edu
Fall, 2010
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Datapath for Branch Instructions
beq rs, rt, offset
if (Rrs Rrt) then PC ? PC4
s_extend(offsetltlt2)
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Datapath More Detailed View
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Simple Implementation

• Include the functional units we need for each
  instruction

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RTL Code for MIPS add

• Fetch
• Instruction ROMPC, PCPC4
• Read Operands
• ALUOp1 Registersrs-value,
• ALUOp2 Registersrt-value
• Add
• ALUOut ALUOp1ALUOp2
• Write Result
• Registersrd-value ALUOut

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Datapath Components for MIPS add
add R1, R2, R3
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Datapath Connections for MIPS add
add R1, R2, R3
Interconnections
What is missing?
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Critical Path for MIPS add
add R1, R2, R3
CLK
Interconnections
Critical path
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Datapath Components for MIPS lw/sw
lw R1, -100(R2) sw R1, -100(R2)
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ROM
Instruction Memory
REGISTERS
Data Memory
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Connections for lw
lw R1, -100(R2)
ALU
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ROM
Instruction Memory
REGISTERS
Data Memory
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Critical Path for lw
lw R1, -100(R2)
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Connections for sw
sw R1, -100(R2)
Data
Port1
WriteRegister
ALU
ReadRegister1
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Port2
ROM
ReadRegister2
Instruction Memory
REGISTERS
Address
DataOut
DataIn
RAM
Data Memory
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Critical Path for sw
sw R1, -100(R2)
Data
Port1
WriteRegister
ALU
ReadRegister1
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Port2
ROM
ReadRegister2
Instruction Memory
REGISTERS
Address
DataOut
DataIn
RAM
Data Memory
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Datapath Connections for MIPS add and lw
add R1, R2, R3
CLK
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Datapath Connections for MIPS add and lw
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Combined Datapath R-Type and Load/Store
Instructions
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Combined Datapath Executing an R-Type
Instruction
add rd,rs,rt
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Combined Datapath Executing a load instruction
lw rt,offset(rs)
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Combined Datapath Executing a store instruction
sw rt,offset(rs)
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Summary

• Read Ch B.7-9