Digital System Design Using

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• Digital System Design Using
• VHDL
• for
• VI Sem (ECE,TCE)
• By
• K.S.GURUMURTHY M.E, PhD
• UVCE, Bangalore University
• Bangalore-1
• drksgurumurthy_at_gmail.com

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XILINX-3000 SERIES FPGA (contd..)
PROGRAMMABLE INTERCONNECTS

• GENRAL PURPOSE
• DIRECT INTERCONNECTIONS BETWEEN ADJACENT
• CELLS
• VERTICAL HORIZONTAL LONG LINES

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GENERAL PURPOSE INTERCONNECTS
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DIRECT INTERCONECTS BETWEEN ADJACENT CLBs
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VERTICAL AND HORIZONTAL LONG LINES
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4000 series CLB
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4000 SERIES I/O BLOCK
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Designing with FPGAs
Steps

• Draw a Block diagram of the digital system.

• Construct the SM chart for the same.

• Write the corresponding VHDL code for the chart

• Simulate and debug the VHDL code. Make necessary
  changes

• Synthesise the code to generate the net list.

• Run a partitioning program.This will map the
  logic on to CLB.

• Run the automatic place route program

• Run a program to generate the bit pattern
  needed for
• programming

• Down load the program to the FPGA

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XILINX DESIGN FLOW
Start
Prelayout simulation
Design entry
P R
To xnf
Back annotated Netlist with delays
.XNF Net list
Netlist with Unit delays
Netlist without delays
.XNF net list
Create Programming file
Make bits
Partitioning into CLBs
xmake
.BIT file
10110.
.LCA Net list
To FPGA or EPROM
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EPROM Connections for LCA Initialisation
DATA
F P G A
EPROM (contains Configur- ationion Data)
ADDRESS
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Complex Programmable Logic Devices (CPLDs)
AGENDA

• Altera MAX 7000 series CPLDs

Macro cell, I/O Control Block

• Altera FLEX 10K Series CPLDs

Block Diagram, Logic Array Block Logic
Element Embedded Array Block

• Summary

• Conclusion

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Input/ Gclk
Input /Gclrn
Input/OE1
Input /OE2
I/O Con trol Blo ck
I/O Con trol Blo ck
Macro cells 1-8
L A B A
L A B B
36
Macro cells 17-24
8-16
8-16 I/O Pins
8-16 I/O Pins
36
8-16
Macro cells 9-16
Macro cells 25-32
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8-16
8-16
L A B C
L A B D
I/O Con trol Blo ck
I/O Con trol Blo ck
Macro cells 49-56
Macro cells 33-40
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36
8-16 I/O Pins
8-16
8-16 I/O Pins
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8-16
Macro cells 57-64
Macro cells 41-48
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16
8-16
8-16

Altera 7000 series Architecture for 7032,
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MACROCELL FOR EPM7032,7064DEVICES
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Vcc
I/O Control Block for EPM 7032
OE1n
0
OE2n
0
Gnd
I/O
.
From Macrocell
To PIA
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Flex10k device block diagram
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FLEX 10K LOGIC ARRAY BLOCK
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FLEX 10K LOGIC ELEMENT
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FLEX 10K EMBEDED ARRAY BLOCK
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