Non Pipelined Read and Write

1
Non Pipelined Read and Write
T1 T2 Ti
T1 T2 Ti
T1
CLK ADDR ADS NA CACHE W/R BRDY
DATA DP PCHK
VALID
VALID
INVALID
INVALID
TO CPU
FROM CPU
TO CPU
FROM CPU
Figure 6-7. Non-Pipelined Read and Write
2
Non Pipelined Read and Write w/ Wait States
T1 T2 T2 Ti
T1 T2 T2 T2
CLK ADDR ADS NA CACHE W/R BRDY
DATA/DP PCHK
VALID
VALID
TO CPU
FROM CPU
Figure 6-8. Non-Pipelined Read and Write with
Wait States
3
Basic Burst Read Cycle
T1 T2 T2
T2 T2 Ti
CLK ADDR ADS CACHE W/R KEN BRDY
DATA/DP PCHK
VALID
TO CPU
TO CPU
TO CPU
TO CPU
Figure 6-9. Basic Burst Read Cycle
4
Slow Burst Read Cycle
T1 T2 T2 T2
T2 T2 T2 T2
CLK ADDR ADS CACHE W/R KENBRDY
DATA/DP PCHK
TO CPU
TO CPU
TO CPU
TO CPU
Figure 6-10. Slow Burst Read Cycle
5
Basic Burst Write Cycle
T1 T2 T2
T2 T2 Ti
CLK ADDR ADS CACHE W/R BRDY DATA/
DP PCHK
VALID
FROM CPU
FROM CPU
FROM CPU
FROM CPU
Figure 6-11. Basic Burst Write Cycle
6
Inquire Cycle that Misses Cache
T1 T2 T2 Ti
Ti T1 T2
CLK ADS W/RBRDY DATA AHOLD EADS ADDR
AP INV HIT HITM APCHK
TO CPU
FROM CPU
FROM CPU
TO CPU
FROM CPU
FROM CPU
TO CPU
Figure 6-24. Inquire Cycle that Misses the
Pentium Processor Cache
7
Inquire Cycle that Invalidates non-M-state Line
T1 T2 T2 Ti
Ti T1 T2

• CLK
• ADS
• W/R
• BRDY
• DATA
• AHOLD
• EADS
• ADDR/AP
• INV
• HITHITM
• APCHK

TO CPU
FROM CPU
FROM CPU
TO CPU
Figure 6-25. Inquire Cycle that Invalidates a
Non-M-State Line
8
Inquire Cycle that Invalidates M-state Line
1 2 3 4
5 6 7 8
9 10 11 T2 T2
Ti Ti T1 T2
T2 T2 T2 Ti
Ti
CLK ADS CACHE W/R BRDY DATA AHOLD EADS
ADDR INV HIT HITM
to CPU
fr CPU
fr CPU
fr CPU
fr CPU
to CPU
Figure 6-26. Inquire Cycle that Invalidates
M-State Line