Sequential Analysis and Design

1
Sequential Analysis and Design

• ELEC 311
• Digital Logic and Circuits
• Dr. Ron Hayne
• Images Courtesy of John Wakerly and Prentice-Hall

2
State Machine Example
3
State Table ? State Diagram
00
01
11
10
4
State Table ? State Diagram
5
State Table ? State Diagram
0/0
1/0
00
01
11
10
6
State Table ? State Diagram
7
State Table ? State Diagram
0/0
1/0
0/0
00
01
0/0
1/0
1/0
0/1
11
10
1/0
8
Timing Diagram
1
CK
0
1
X
0
1
Q1
0
1
Q2
0
1
Z
0
9
State Table
10
State Diagram
0/0
1/0
0/0
00
01
0/0
1/0
1/0
0/1
11
10
1/0
11
Timing Diagram
1
CK
0
1
X
0
1
Q1
0
1
Q2
0
1
Z
0
12
State Table
13
State Diagram
0/0
1/0
0/0
00
01
0/0
1/0
1/0
0/1
11
10
1/0
14
Timing Diagram
1
CK
0
1
X
0
1
Q1
0
1
Q2
0
1
Z
0
15
State Table
16
State Diagram
0/0
1/0
0/0
00
01
0/0
1/0
1/0
0/1
11
10
1/0
17
Timing Diagram
1
CK
0
1
X
0
1
Q1
0
1
Q2
0
1
Z
0
18
State Table
19
State Diagram
0/0
1/0
0/0
00
01
0/0
1/0
1/0
0/1
11
10
1/0
20
Timing Diagram
1
CK
0
1
X
0
1
Q1
0
1
Q2
0
1
Z
0
21
State Table
22
State Diagram
0/0
1/0
0/0
00
01
0/0
1/0
1/0
0/1
11
10
1/0
23
Timing Diagram
1
CK
0
1
X
0
1
Q1
0
1
Q2
0
1
Z
0
24
State Table
25
State Diagram
0/0
1/0
0/0
00
01
0/0
1/0
1/0
0/1
11
10
1/0
26
Timing Diagram
1
CK
0
1
X
0
1
Q1
0
1
Q2
0
1
Z
0
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State-Machine Design

• Construct a state/output table
• Assign state-variables
• Construct a transition table
• Derive excitation equations
• Derive output equations
• Draw a logic diagram

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Design Example

• Sequence Detector (0101)
• Single Input (X)
• One bit per clock cycle
• Single Output (Z)
• Detects last 4 bits of sequence
• Non-resetting Mealy machine

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State/Ouptut Table
30
State/Ouptut Table
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State/Ouptut Table
32
State/Ouptut Table
33
State/Ouptut Table
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State Assignment

• Initial state which machine can be easily forced
  into by reset
• Minimize number of state variables that change on
  each transition
• Exploit symmetries

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Transition/Ouptut Table
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Excitation/Ouptut Maps
D1 (X Q2) (X' Q1 Q2') D2 X' Z X
Q1 Q2
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Summary

• Sequential Analysis
• State Table
• State Diagram
• Timing Diagram
• Sequential Design
• State/Output Table
• Transition Table
• Excitation Output Equations
• Logic Diagram