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Towards Next generation INCODE

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2001: To popularize FPGA design among other engineering colleges in ... 16 KB on-chip static RAM and 256KB on-chip Flash program memory. In-system programming. ... – PowerPoint PPT presentation

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Title: Towards Next generation INCODE


1
Towards Next generation INCODE
  • Embedded System Group
  • IIT Delhi

2
Chronology of INCODE
  • Early 90s CSE started using FPGA as a part of
    student projects.
  • 1995 A regular laboratory curricula was
    introduced.
  • 1999 INCODE was developed.
  • 2001 To popularize FPGA design among other
    engineering colleges in India the technology was
    transferred to M/S VPL InfoTech and consultant
    Ltd.

3
Motivation behind INCODE development
  • A versatile kit which can be used for laboratory
    experiments.
  • A Low cost board which can be used as teaching
    aids.
  • Incorporate latest techniques and methodologies
    in the curriculum.

4
The INCODE Hardware
5
The INCODE Software
6
A closer look on the Design.
Personal Computer with INCODE Software and
digital hardware design tools
Serial Communication
FPGA
1
8051
2
RAM ROM
Peripheral board
INCODE board
7
Two Major features
  • Downloading the bit file to the targeted FGPA
  • Foremost task to be performed by the tool is to
    transfer the design to the FPGA, which is
    achieved by downloading the bit file.
  • Hardware Software co-design environment.
  • Providing ways for hardware software interaction.

8
Downloading the Design on FPGA
  • Mode of download
  • Slave Serial mode
  • FPGA is slave and bit file is serially
    transferred.
  • Master Serial mode
  • FPGA is Master and bit file is serially
    transferred.
  • Select Map Mode
  • Bit file is transferred one byte at a time.
  • Boundary Scan mode
  • Through JTAG cable

9
Slave serial configuration mode flow chart
Source Xilinx datasheet
10
Hardware software Co-Design
  • Data can be transferred from the PC to the
    Hardware design in the FPGA.
  • Software functions can be downloaded and run on
    the 8051 microcontroller.

11
Why New board design?
  • 4000 family FPGA production and support has been
    discontinued.
  • Bigger designs can not be implemented.
  • Multiplatform Tool.
  • To add more features to the tool and keep the
    pace with latest technology.

12
Next version
  • Enhancements were continuously done by adding the
    library components and case studies.
  • To incorporate the bigger designs the hardware
    was required to upgraded.
  • New board with Virtex-E family FPGA was designed
    in 2003.

13
The boards together
14
Problems
  • The working version of the software's were
    misplaced.
  • The Virtex-E board design did not considered the
    fact that it is a low voltage design.

15
Solutions
  • The Firmware for 8051 was re-written.
  • Code was written in C using Keil cross compiler.
  • Is an application running over on RTOS (RTX51
    Tiny).
  • The Hardware was interfaced with a ARM7 based
    microcontroller LPC2129 for configuration.
  • Testing is in progress.

16
Requirements for new board
  • Advance FPGA
  • Advance microcontroller
  • Faster communication channel
  • Better Co-design environment

17
Few compressions .
18
Proposed Block diagram for new board design
Personal Computer with INCODE new
multiplatform Software and digital hardware
design tools
Parallel/USB Communication
Virtex-E Family FPGA
ARM7 based microcontroller
R A M
RAM
INCODE board
Peripheral board
19
Configuration Select Map Mode
  • The selectMAP Mode is the fastest configuration
    option.
  • Byte wide data is written into FPGA with a busy
    flag controlling the flow of data.
  • An external data source provides the byte stream,
    CCLK, CS, and Write signal. If BUSY is asserted
    high by the FPGA, the data must be held until
    BUSY goes low.
  • Data can also be read using the selectMAP mode.

Source Xilinx datasheet
20
LPC2294 ARM7 based 32-bit Microcontroller
  • 32-bit ARM7 microcontroller in a 144 pin package.
  • 16 KB on-chip static RAM and 256KB on-chip Flash
    program memory.
  • In-system programming.
  • 112 general purpose I/O pins.
  • Low voltage operations.
  • On-chip peripherals like 10-bit ADC, 2 serial
    ports, CAN interfaces.

21
Towards next generation INCODE.
  • Goals
  • Enhanced features.
  • Multiplatform Tool.
  • Achievements
  • Interfaced the Virtex-E with ARM7 based LPC2129
    microcontroller.
  • Written Code to configure the FPGA in slave
    serial mode.
  • Component study has been done.
  • To be done
  • Freeze the specifications.
  • Detailed design.
  • Documentation (Manuals, Website).

22
Thank you
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