NCU EE683 VLSI Testing HW1

1
NCU EE683 - VLSI Testing HW1

• Due Date March 21, 1999
• Do the following question on different figures
  (one for each sub questions)
• Mark all the faults.
• Show the equivalent and dominant relations.
• Drops the faults according to the equivalent and
  dominance relation.
• Divide the circuits into fanout free regions.
• Show and check point faults (both s-a-1 and s-a-0
  on all check points)
• Drops the check point faults s according to the
  equivalent and dominant relations.
• Homework guide lines
• Use this file as the the emplate and compiles all
  your homework in one file.
• Down load the file and Go to the ?? to change
  NCU-EE-CCSU to NCU-EE-??-??.
• Your homework file should be named
  TESTxxxx.ppt, xxxx is the last four digits of
  your ID number.
• Print out the file in 2-per-page format and
  submit it.

sa0
sa1
2
NCU EE683 - VLSI Testing HW2-1

• The left figure shows the relationship between
  fault coverage T, yield Y, and defect level DL.
• Suppose that the price for the chip is as
  follows.
• Chip fabrication cost 10
• Chip sale price 15
• Defect chip penalty 50
• The relationship between the fault coverage and
  yield is (high yield)
• The test cost is
• What is the optimal fault coverage to make the
  most profit?
• What is the optimal fault coverage if the yield
  is (low yield)
• Hint the T is a variable, derive a profit
  equation as function of T. Then, find a T that
  maximize the profit.

G
N
Total Fabricated
Test
Field
F
Rejected
D
Defects
N Total Fabricated F Tested Fail G Tested
Good D Defects DL Defect Level in DPM DPM
Defects per Million T Fault Coverage
3
NCU EE683 - VLSI Testing HW2 - 2
1 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1
1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 0
0 1 0 0 1 0 0 1 0 0 1 0 0 0

• The above LFSR is able to generate all possible
  combinations except all zeros.
• Modify the circuit so that it can generate all
  possible combinations including (0000). Hint
  find a slot to insert 0000 and modify the
  feedback circuit to make the transition possible.
  This is so called nolinear feedback shift
  register.

4
NCU EE683 - VLSI Testing HW2 - 3

• The exhaustive test patterns are run from 1000 to
  0100 (as show in the previous page).
• Use the following methods to do response
  compression and verification. (You must draw the
  circuit diagram for each case)
• Ones count
• Transition count
• Signature Analysis (LFSR) (with the same
  polynomial)
• For a give method do the following
• Derive the output sequence
• Derive the signature
• Derive the aliasing probability.
• For the fault A stuck_at_0, do the following.
• Derive the output sequence
• Derive the signature
• Check if the fault is detectable.

D0
D1
D2
D3
A
SA