FPGA PIN CONFIGURATION

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FPGA PIN CONFIGURATION
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Design FloorPlan

• Actual layout of MP2 on Virtex FPGA.
• Color regions correspond to used resources
• Design currently uses roughly 27 of Slices.

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Design FloorPlan
Wrapper_app (Shown in Black)
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Design FloorPlan
CAM2_entry and CAM2_Mask (Shown in Black)
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Design FloorPlan
Wrapper_apps State Machine (Shown in Black)
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Design FloorPlan
Regex_app (Shown in Black)
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Design FloorPlan
Wrappers (Shown in Black)
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Closer View (Wrapper_Apps State Machine)

• Each block represents one SLICE