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Submicron Verification Challenges

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speed. Background. Been available for many years. A timing defect test pattern. Used so far to test very high speed devices & very accurate goals ... – PowerPoint PPT presentation

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Title: Submicron Verification Challenges


1
SubmicronVerificationChallenges
Uri Gruenbaum
2
Presentation Flow Chart
Intro
Intro
_at_speed
Problems
Case study
3
Presentation Progress
Intro
_at_speed
Problems
Case study
4
Intro
Intro
  • Whats going on?
  • IC features continue to shrink.
  • Fabrication processes under 130 nm
  • Different size generate different faults.
  • The faults Distribution is different
  • Good old Stuck-at pattern isn't Good enough.

_at_Speed
Competition
Case study
5
Intro
Intro
  • In 180 nm we had
  • Stack at pattern
  • Standard memory BIST (Built in self test)
  • Iddq
  • You combine all of them and you get a coverage of
    100

_at_speed
problems
Case study
6
Intro
Intro
  • In 130 nm and less we have
  • Higher frequencies.
  • Different physical properties.
  • Much more timing defects

_at_speed
problems
Case study
7
Intro
Intro
  • Did you know?
  • Research from LSI Logic and Intel shows that the
    population of timing defects for nanometer
    designs is 2

_at_speed
problems
Case study
8
Intro
Intro
  • Example
  • 130 nm fabrication process
  • Yield average of 70
  • Static fault testing coverage of 100
  • 2 left unchecked
  • 50 of them on average are ok
  • We will have a defect rate of 0.7
  • DPM of 7000

_at_speed
problems
Case study
Unacceptable
9
Presentation Progress
Intro
_at_speed
Problems
Case study
10
_at_speed
  • Background
  • Been available for many years
  • A timing defect test pattern
  • Used so far to test very high speed devices
    very accurate goals

Intro
_at_speed
problems
Case study
11
_at_speed-before scan
Intro
_at_speed
Competition
Our Solution
What next?
clock
12
_at_speed- scan insertion
Intro
_at_speed
Competition
Our Solution
What next?
SI
SO
SE
clock
13
_at_speed-shift phase
Intro
_at_speed
problems
Case study
SI
1
SO
SE 1
clock
SI
clock
14
_at_speed-shift phase
Intro
_at_speed
problems
Case study
15
_at_speed-capture
Intro
_at_speed
problems
Case study
16
_at_speed-capture
Intro
_at_speed
problems
Case study
17
_at_speed-shift phase
Intro
_at_speed
Problems
Case study
0
18
_at_speed Vs Stuck at
Intro
_at_speed
problems
Case study
19
_at_speed-Accurate clocks
Intro
_at_speed
  • There can be variations between the testers
    clock and the PLL clocking

problems
Case study
20
_at_speed - solution
  • One solution is having the ATPG (automatic test
    pattern generation) to decide which clock is
    necessary

Intro
_at_speed
problems
Case study
21
Presentation Progress
Intro
Market
Problems
Case study
22
Problems
  • Test patterns for transition faults are not as
    efficient as for stuck at faults
  • Transition faults test 5 times in size as a
    static fault test
  • When combined ,expensive tester reloads is
    performed

Intro
Market
Problems
Case study
23
Problems
  • An interesting fact

Intro
Market
Problems
Case study
  • Transition test pattern detect a significant
    percentage of stack at faults

Starting to get the picture?
24
Problems
  • If you need to add TFP reduce the number of
    SAP.
  • Do it by creating the TAP first and the SAP next.

Intro
Market
Problems
Case study
25
Presentation Progress
The Need
_at_speed
Problems
Case study
26
Case study
The Need
  • The goal
  • Getting the best possible test coverage
    without doing expensive tester memory reloads.

Market
problems
Case study
27
Case study
The Need
  • Characteristic of test design

Market
problems
Case study
28
Case study
The Need
  • For the design, the test requirements are

Market
  • Tester can hold up to 10,000 test patterns
  • The highest priority is to get max coverage for
    SAF
  • The test coverage for the TF must be as high as
    possible as long as it still fits the memory.

problems
Case study
29
Case study
The Need
  • Result

Market
problems
Case study
30
Case study
  • Truncating the TDF results in a significant lost
    in transition coverage
  • TDF coverage 85.14 63.93
  • Clearly not ideal

The Need
Market
problems
Case study
31
Case study
The Need
  • How can we improve it?

Market
problems
  • Recognize that for each TDF its equivalent SAF
    is also detected
  • remove the least effective patterns

Case study
32
Case study
The Need
  • Result

Market
problems
Case study
33
Case study
The Need
Market
problems
Case study
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