A SelfTest Methodology for AtSpeed Test of Crosstalk in Chip Interconnects

1
A Self-Test Methodology for At-Speed Test of
Crosstalk in Chip Interconnects

• Xiaoliang Bai , Sujit Dey
• Department of Electrical and Computer
  Engineering
• University of California, San Diego
• xibai,dey_at_ece.ucsd.edu
• Janusz Rajski
• Mentor Graphics Corporation
• janusz_rajski_at_mentorg.com

2
Outline

• Motivation
• Fault Model
• Methodology and designs of Self-Test Structures
• Applying Self-Test Methodology and Validation
• Conclusion and future work

3
Motivation

• DSM Technologies will lead to increasing
  noise/interference

• Design for crosstalk cannot cover all possible
  process variations Need for manufacturing
  testing
• Crosstalk errors most significant in high-speed
  circuits and prohibitive cost of external tester
  At-Speed Self-Test
• Crosstalk effects most significant in long
  interconnects
• Cuviello, Dey, Bai, Zhao Fault Modeling and
  Simulation for Crosstalk in System-on-Chip
  Interconnects, ICCAD 1999

At-speed self-test of crosstalk in SoC
interconnects
4
Fault Model

• Fault types ve glitch gp, -ve glitch gn,
  rising delay dr and falling delay df
• Fault effect on victim Yi
• All other wires act as aggressors, affect Yi via
  their coupling capacitances

5
Maximal Aggressor Tests

• For a set of N interconnects, 4N faults, and 8N
  test vectors
• MA tests can detect all crosstalk defects due to
  coupling-capacitances

Based on pre-determined MA Tests, deterministic
self-test of SoC interconnects using embedded
structures
6
Outline

• Motivation
• Fault Model
• Methodology and designs of Self-Test Structures
• Applying Self-Test Methodology and Validation
• Conclusion and future work

7
Issues for Self-Testing Interconnects
Cache Bus
Cache
16
UART
UDL
Video
Encoder
Arbiter
Interface
6
4
16
32
8-bit Peripheral Bus
Bridge
32-bit Processor Bus
8
32
16
8
16
Bus Arbitrator
External
Arbiter
BIU
RAM2
RAM1
DMA
UDL
8
External Bus

• Objective Select a minimal number of Test
  transactions which cover all the operational
  transactions
• Crosstalk effect depends on coupling caps, and
  driver/receiver

• Selecting and scheduling test transactions

Core-to-Core transactions

• Bi-directional transactions,

• Dynamic bus sizing,

Split bus transactions

• Test interconnects using embedded self-test
  structures
• On-chip test generators, error detectors, test
  controller

8
Design of Test Generator
9
Design of Error Detector
Core I/O
Core
n
n
n
n
Bus
10
Design of Global Test Controller
Last Transaction Counter
Tmode0
Idle
Tmode0
NO of Vectors Enables
Trans Rst
Tmode0
Transaction Counter
Trans Inc
0 1 0 0 0 1 1 0
Trans Rst Vector Rst
Vector Rst
Vector Counter
Test Clk
Transactions Complete1
Next Trans.1
Complete
Trans Inc Vector Rst
Next Transaction
Wait
Test and Vector Counter Log
Test Count
Vector Count
Generator, Analyzer Global Enables
Analyzer Error Flags
Tmode
Test Complete
Flag0
Flagk
En0
Enm
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Outline

• Motivation
• Fault Model
• Methodology and designs of Self-Test Structures
• Applying Self-Test Methodology and Validation
• Conclusion and future work

12
Applying Self-Test Methodology to a DSP

• CMUDSP, corresponding to Motorola 56002 DSP core
• Components AGU, ALU,PCU,Bus Switch
• Buses Address buses XAB,YAB,PAB, Data
  BusesXDB,YDB,PDB,GDB

13
Applying Self-Test Methodology to a DSP

• Test transactions
• selected fromoperational transactions
• Global Test Controller

CMU DSP
Large area overhead due tosmall components
Interconnect area not included
14
Validating Self-Test MethodologyUsing high-level
Crosstalk Defect Simulation
high-level crosstalk defect simulation

• Spice-level simulation for complete chip not
  feasible
• HDL Level simulation enviroment
• HDL models of Test Generators and Error Detectors
• Interconnect Models simulate injected faults
  using test vectors, and generate digitized error
  effects

15
Validation of Self-Test Methodology

• High-level DSM Error Models used to simulate
  logic components, test structures, and
  interconnects in HDL
• Self-test Methodology implemented in DSP circuit
  validated with randomly injected cross-coupling
  defects

16
Conclusions and Future work

• Methodology enabling self-test of crosstalk
  defects in chip interconnects
• Deterministic self-test with 100 FC
• Applied to a real circuit, and validated
• Potential disadvantage high area overhead
• Future
• Minimize area overhead develop crosstalk
  self-test method which uses processor cores as
  test generators, error detectors, and test
  controllers
• Develop system-level mixed-signal crosstalk fault
  simulation
• high speed, accurate