A 24GHz PhasedArray Transmitter in 0'18mm CMOS

1
A 24GHz Phased-Array Transmitter in 0.18mm CMOS

• A. Natarajan, A. Komijani, and A. Hajimiri
• California Institute of Technology

2
Outline

• Phased Array Overview
• Phased Array Transmitter Architecture
• 24GHz Phased Array Transmitter - Design
• Measurement Results
• Conclusion

3
Motivation
Multiple Antenna Systems

• Receive and transmit diversity increases data
  rates.

l/2 in air
l/2 on PCB
Antenna Length, Spacing between
Antennas proportional to l

• System size decreases as frequency increases.
• Large bandwidths available at higher
  frequencies.
• However, smaller antenna area ? lower collected
  power.

• Integrate on silicon based processes to lower
  cost.

4
Phased Array Benefits
Silicon-based RF and Baseband Circuits

• At Receiver, array gain helps reject
  interferers. SNR is
• improved by 10.log N dB.
• In Transmitter, beamforming reduces transmitter
  power
• requirements and creates less interference.
• Directivity enables higher frequency reuse.

5
Higher Frequencies?
PTX50mW

• Assumptions
• A l2 or 1/f2
• fT 120GHz
• Distance 10m
• BW f0 / 100
• Omni-directional antenna
• Noise Figure scales linearly with frequency

NF_at_24GHz4.78dB
NF_at_60GHz7.78dB
NF_at_24GHz10dB
Shannon Capacity Gbps
NF_at_60GHz13.7dB
Frequency GHz
6
24GHz Spectrum

• ISM Band Wireless Communication
• Bandwidth 250MHz,
• Field Strength lt 2.5 V/m _at_ 3m distance
• ? EIRPavg 26dBm
• Antenna gain gt 33dB or Beamwidth lt 3.5.

• Vehicular Radar System
• Bandwidth 7GHz,
• EIRP -41.3dBm/MHz ? -3dBm across 7GHz,
• Radiation 30 above horizontal attenuated by
• more than 25dB.

EIRP Effective Isotropic Radiated Power
7
Phased Array Transmitter
Higher power at targeted receiver due to coherent
addition of signals.
Delay
Lower interference due to incoherent addition of
signals.
Beam steering acheived by varying delay in each
element
With N element TX, if each element radiates P
Watts, Effective radiated power in target
direction N2.P Watts.
8
Phased Array Architecture

• Ideally, true-time delay needed to
• compensate for propagation delay.
• For narrowband systems, time delay
• approximated by phase shift.

Narrowband Approximation
RF Delay
Equivalent IF and LO delay
LO Phase Shift
Phased Array Architecture Evolution
9
4 Element TX Array Pattern

• Plot for Fo 0, 22.5, 45,67.5, 90,, 337.5

• For a 4 element array, phase shift resolution of
  22.5 is sufficient.
• Scanning resolution is less than 10 in the
  normal direction.
• Beam becomes wider for a more oblique beam
  direction.

10
Outline

• Phased Array Overview
• Phased Array Transmitter Architecture
• 24GHz Phased Array Transmitter - Design
• Measurement Results
• Conclusion

11
Frequency Plan
On-chip power amplifiers and VCO make direct
upconversion unsuitable.

• Two step upconversion
• architecture,
• LO frequencies 4.8GHz
• and 19.2GHz,
• Generate both LO from a
• single synthesizer using
• divide-by-four.

• Quadrature upconversion
• for image attenuation,
• Image at 14.4 GHz
• further attenuated by
• tuned stages at RF.

12
TX Architecture

• Integrated CMOS PA, with 50O output matching, in
  each element,
• 16-phase 19.2GHz VCO generates multiple phases
  for LO phase shifting,
• Phase selectors in each path programmable using
  digital serial interface,
• On-chip synthesizer generates LO frequencies
  from 75MHz reference.

13
TX Die Photograph
6.8mm
2.1mm

• Process 0.18µm CMOS transistors in BiCMOS
  process.
• NMOS Transistor fT 65GHz.
• 5 metal layers Top 2 metal layers are 4mm and
  1.25mm thick.

14
Outline

• Phased Array Overview
• Phased Array Transmitter Architecture
• 24GHz Phased Array Transmitter - Design
• Measurement Results
• Conclusion

15
Digitally Tunable Loads

• 5 off-tuned load _at_ 24GHz
• ? load off-tuned by 1.2GHz.
• Switchable capacitors ensure
• right center frequency.
• Compensate for simulation
• errors and process variations

16
Balun

• Differential to single-ended conversion at PA
  input.
• Single-turn to reduce capacitive coupling to
• substrate.
• Insertion loss of 1.5 dB.

17
Power Amplifier

• 2 stage PA with on-chip 50O
• output matching
• RC network at input of each stage
• ensures low frequency stability

Transmission line based matching network reduces
loss and improves on-chip PA isolation

• A. Komijani, et al., A 24GHz, 14.5dBm
  fully-integrated power amplifier in 0.18mm CMOS
  ,CICC 2004.

18
Transmission Line Structure

• Ground plane beneath signal line ?High
  Capacitance, C,
• Patterned ground plane forces return current
  through coplanar ground lines that are farther
  away ? High Inductance, L,
• Larger L and C lead to lower wave velocity ?
  lower ? and therefore smaller matching network.
  (? _at_ 24GHz 3mm)
• Wide signal and ground lines ? lower loss per
  unit length. (0.4dB/mm)
• Smaller loss per unit length and shorter lengths
  lead to lower total loss.

• T.S.D. Cheung, et al., On-chip interconnect for
  mm-wave applications using an all-copper
  technology and wavelength reduction, ISSCC 2003.

19
19.2GHz Synthesizer
19.2-GHz
Charge Pump
Loop Filter
VCNTRL
fref
PFD
fout16 phases
75-MHz
one VCO phase
4.8GHzI
4
64
4.8GHzQ

• Third order loop 7MHz loop bandwidth.
• Similar design to A fully integrated 24-GHz
  eight-element
• phased-array receiver in silicon, X. Guan, H.
  Hashemi, and A. Hajimiri,
• JSSC, Vol. 39, Issue 12, Dec. 2004.

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16 Phase VCO

• 19.2GHz CMOS VCO consists of 8 differential
  amplifiers in a ring
• structure.
• 16 equally spaced phases with steps of 22.5 are
  generated.
• Amplifiers tuned close to wosc due to large tank
  Q.

• J. Savoj and B. Razavi, A 10Gb/s CMOS Clock and
  Recovery Circuit with a Half-Rate Binary Phase-
• Frequency Detector, IEEE JSSC, vol. 3, no. 1,
  pp. 13-21, Jan 2003.
• H. Hashemi, X. Guan, and A. Hajimiri, A Fully
  Integrated 24GHz 8-path phased-array receiver in
  silicon,
• ISSCC 2004.

21
Phase Selection
LO Q
LO I
LO I
LO Q
Sign Selector
Sign Selector
Control Bit
Control Bit
8 Phase LO 19 GHz Differential Signal
Dig. Phase Selection
Dig. Tuning Control

• Two stage phase selection.
• First stage selects right LO output differential
  pair for LO I and LO Q.
• Second stage selects the right sign.

22
Phase Selection

• Differential pairs with tail
• current switch select desired
• LO phase in each stage.
• Set of dummy phase selectors
• ensure constant load on VCO
• buffers.

23
Outline

• Phased Array Overview
• Phased Array Transmitter Architecture
• 24GHz Phased Array Transmitter - Design
• Measurement Results
• Conclusion

24
4 Path Test PCB
Baseband Input, I and Q
Digital Interface
VDD
TX Outputs
TX Outputs
VDD
Divider Output (Monitoring)
75MHz Ref.

• Emphasis on symmetric input and outputs and good
  grounding.
• The PCB design is compatible with planar antenna
  structures.

25
4 Path Test PCB
Chip
GND
Pedestal
PCB

• Ground pedestals minimize ground wirebond
  inductance at PA output.

26
Synthesizer Performance
Tuning Range
Phase Noise (dBc/Hz)
-40
Frequency (GHz)
20.2-GHz
-60
19.2-GHz
-80
20log(28)
-100
-120
75-MHz reference
-140
-160
100
10k
1M
100M
Offset Frequency Hz

• Synthesizer has a frequency locking range of
  2.1GHz,
• Phase noise limited by noise from 75MHz
  reference.

27
PA Performance
Output Match
Output Power and Gain
Two Tone Test
PoutdBm
PindBm
28
Measurement Setup
The variable phase shifters emulate the
propagation delay in each path.
29
Beam Forming Performance
30
QPSK Spectrum
100 Mb/s QPSK
500 Mb/s QPSK
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Test Setup - II
Baseband input signal to the I channel.
Off-chip LO is used to downconvert the output and
to generate the 75MHz reference for the frequency
synthesizer.
Divide by 320
LO 24GHz
Mixer
32
Eye Diagram 250Mbps BPSK
BASEBAND OUTPUT EVM 9.7 (Limited by the
off-chip mixer)

• Single Channel (I) Output _at_ 250 Mbps.

33
Eye Diagram 500Mbps BPSK
BASEBAND OUTPUT EVM 9.8 (Limited by the
off-chip mixer)

• Single Channel (I) Output _at_ 500 Mbps.

34
Phased Array Performance
35
Performance Summary
36
Conclusions

• Multiple antenna systems offer more spectrum
  efficient solutions.
• It is feasible to fully integrate multiple
  antenna systems at 24GHz on silicon-based
  processes.
• LO path phase-shifting architecture is well
  suited for integrated phased arrays at high
  frequencies.
• The first fully-integrated phased-array
  transmitter at 24GHz, using 0.18mm CMOS, has been
  demonstrated.

37
Acknowledgements

• Lee Center for Advanced Networking, Caltech,
• X. Guan, B. Analui, M. Morgan, E. Afshari and N.
  Wadefalk of Caltech,
• H. Hashemi, formerly of Caltech, now with USC,
• IBM T. J. Watson for chip fabrication,
• Software Assistance Cadence, Agilent
  Technologies, and Zeland Software, Inc.