Y 120 "F SS"

1
?Y 120 "??F???? S?????S?"

• ???µ? t??a?a? p??spe?as??
• (Random Access Memory - RAM)

2
???ade? µ??µ?????µ? t??a?a? p??spe?as?? RAM

• S?????? ??ta??? ap????e?s?? s?et??a ?????µata
  ??a e?s?d?-e??d? ded?µe???.
• ? p??spe?as? ???eta? se ?p??ad?p?te ?es? gt
  random access
• ?? p????f???e? ap????e???ta? ? a?a?a????ta? ?at?
  ?µade? bits p?? ???µa???ta? words (?e?e??).
• ??a ?e?? µp??e? ?a pa??sta?e? ??a? a???µ?, µ?a
  e?t???, ??a? ? pe??ss?te???? ?a?a?t??e?
• ? ep????????a µ?a? µ??µ?? µe t?? e?? ??sµ?
  ???eta? µe
• G?aµµe? e?s?d?? ?a? e??d?? ded?µe??? (data input
  ?a? output lines).
• G?aµµe? ep?????? d?e????s?? (Address selection
  lines)
• G?aµµe? e?e???? (control lines)

3
?as??e? ?e?t?????e? t?? µ??µ?? t??a?a?
p??spe?as???????sµ?? ?e?t??????? ????af?? ?a?
??a??s??

• ??? e??a? ?? ßas??e? ?e?t?????e? t?? µ??µ??
  t??a?a? p??spe?as??
• ????af? (Write) ded?µe???
• ?etaf??a t?? d?e????s?? t?? ep???µ?t?? ?es?? st??
  ??aµµe? d?e????s??
• ?etaf??a t?? ded?µe??? st?? ??aµµe? e?s?d??
  ded?µe???
• ??e???p???s? t?? s?µat?? e?e???? Write

Read / Write
Chip select CS
Address lines
Valid Address
Data In
4
?as??e? ?e?t?????e? t?? µ??µ?? t??a?a?
p??spe?as???????sµ?? ?e?t??????? ????af?? ?a?
??a??s??

• ??a???s? (Read) ded?µe???
• ?etaf??a t?? d?e????s?? t?? ep???µ?t?? ?e??? st??
  ??aµµe? d?e????s??.
• ??e???p???s? t?? s?µat?? e?e???? Read ( ? Chip
  select)
• A?a???s? t?? ded?µe???

Read / Write
Chip select CS
Address lines
Valid Address
Data Out
Data out
5
??p?? ???µ??

• ??a???a µe t?? µe??d? p??spe?as??
• RAM (Random access Mem.)
• SAM (Sequential access Mem.)
• ??a???a µe t?? d?µ? t???
• Static RAM (pe??e?e? flip-flops)
• Dynamic RAM (pe??e?e? p????te?, ??e?a?eta?
  a?a?e?s? t?? pe??e??µe??? t?? gt refreshing)
• A?a???a µe t?? d?a??e?a ???? t?? pe??e??µe??? t??
• Volatile (???s????? ?a?e? t? pe??e??µe?? µ????
  afa??e?e? ? t??f?d?s?a t??)
• Non-volatile (µ???µ? ap????e?s?)

6
Es?te???? d?µ? t?? RAM

• ??a µ??µ? RAM, m ?e?e?? t?? n bits, ap?te?e?ta?
  ap? m x n d?ad??a ??tta?a ap????e?s?? ?a?
  ?ata????? ap???d???p???t? ??a ep????? µ?a? ap?
  t?? m ?e?e??.
• ?? ßas??? d?ad??? ??tta?? ap????e?s?? fa??eta?
  p?? ?at?

Select
Select
Out
In
?C
R S
Out
In
Q
R / W

• Binary Cell (BC)
• ????? µe?e???
• ????? ??st??/bit
• ????? ?ata?a??s? ?s????
• ?????? ?????? p??spe?as??
• 2 a???p?ste? e?sta?e?? ?atastase??

Read / Write
7
????atastat?? ?d???t?? (Tri-state Buffer)

e
0
x
f
e
x
f
e
1
x
f
?s?d??aµ? ?????µa
G?af??? s?µß??? ????atastat?? ?d???t?
f
e
x
0
0
Z
0
1
Z
1
0
0
1
1
1
???a?a? a???e?a?
8
?esse??? t?p?? t???atastat?? ?d???t?

9
?fa?µ??e? t?? t???atastat?? ?d???t?

• ????p?e?t?? 2 se 1
• ?µf?d??µ?? Buffer

x
f
1
s
x
2
x
y
10
To ßas??? ??tta?? µ?a? SRAM.??a SRAM 2 x 2
11
H es?te???? d?µ? µ?a? RAM 22 x 2
Input lines

2x4
00
01
Address
10
Enable
11
Read/write
Output lines
12
H es?te???? d?µ? µ?a? RAM 2m?n
13
S??des? t?? RAM ICs

• ??a Chip RAM 1024x8
• RAM 1024 x 16

MSB In LSB
8 8
10 Address
8
1k x 8
In Out ADRS CS R/W
8
10
8
8
MSB Out LSB
14
S??des? t?? RAM ICs RAM 4096 x 8
A12 A11 A10A1

In
8
10
8
11 10 01 00
1k x 8
In Out ADRS CS R/W
8
10
Read/Write
8
1k x 8
In Out ADRS CS R/W
8
10
8
1k x 8
In Out ADRS CS R/W
8
10
8
1k x 8
In Out ADRS CS R/W
8
8
10
Out
15
Debouncing
??a??pt?? e??? p???? µ?a? ?ese??
V
??a??pt?? e??? p???? d?? ?ese?? µe
?????µa debouncing
DD
V
DD
R
R
S
Data
Data
R
R
V
DD
16
Sp?????e? (Hazards)??d? Sp???????
1
0
0
0


1
1
Stat???? sp?????a?
1
0


0
1
1
0
???aµ???? Sp?????a?
17
Stat???? Sp?????e? (Hazards)

x
2
p
x
1
f
q
x
3
?????µa µe stat??? sp?????a
x
x
1
2
x
3
00
01
11
10
0
1
1
1
1
1
?????e?s? stat???? sp?????a µe t?? ß???e?a t??
?a?t? Karnaugh
18
???aµ???? Sp?????a?

fx1x2'x3'x4 x1x4
19
Project "SIMON Fall 2000

LEDs
??sa???? ?µfa??s? ?pa?a???? ?a???
Hard
Easy
Reset
Clock
??a??pte? e?sa????? st???e???