Product Overview

1
Product Overview
TEAM W3Digital Voice Processor 525
Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim
(W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5)
Design Manager Abhishek Jajoo
Date 5/3/2006 Final Presentation

• Voice Specific Analog-to-Digital Conversion Chip
• Meeting demands of high quality voice
  applications such as Digital Telephony, Digital
  Hearing Aids and VOIP.

2
Final Presentation Agenda

• Product Background Marketing
• Jarrett Avery
• Algorithm Design Process
• Sean Baker
• Floorplan Evolution Component Layout
• Sherif Morcos
• Top Level Layout Digital Verification
• Amar Sharma
• Analog/Overall Verification, Specs, Summary
• Huiyi Lim

3
Product Background Marketing

• Jarrett Avery

4
Product Background

• Find a Customer
• Complement Current Market Trends
• Develop for Multiple Applications
• Design a Comprehensive Product
• Fulfill classroom design goals
• Include useful features and benefits
• Use Talents of a Diverse Team
• Analog and Digital Design Skills

5
Voice Market

• Target Customers
• IP Telephone Providers
• Vonage, Skype, and CRM
• Government and Security Agencies
• Hearing Aid Producers
• Goal of the Product
• Better-Cheaper Telephone Service (VOIP)
• Secure Private Telephony
• Custom Hearing Aids for Specific Conditions
• More Accurate Speech to Text

6
Specific Applications

• Communication Devices
• Voice Over IP Handsets
• Encrypted Telephony
• Digital Hearing Aids
• Speech Recognition

7
Why Choose DVP-525

• Better than other products on the market
• Superior Features Include
• Precision 1st Order Delta Sigma ADC
• Integrated Butterworth Low-Pass Filter
• Built on 180 nm Technology
• Includes a Min/Max Input Indicator
• Important Benefits
• Low Power Design For mobile applications
• Small Foot Print Fits into larger signal chains
• Resilience to Circuit Noise Optimized to reduce
  interference

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Delta Sigma (?S) Design

• Advantages
• Accurate Conversion, oversamples the input signal
  and filters the desired signal band.
• Filters off unwanted noise in the signal
• Good design for audio applications
• Consists of two part design for the team
• Analog Modulator
• Digital Decimator

9
Algorithm Design Process

• Sean Baker

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?S Algorithm (Analog)
Input from outside world
Lowpass Filter
Filtered analog signal
Bitstream into sinc filter
Delta Sigma Modulator
11
?S Algorithm (Digital)
Bitstream from modulator
Oversampled clock
Nyquist clock
Sinc Filter
Peak Input Indicator
Digital output
Max / Min output
Digital Output
12
Top Level Schematic
13
Design Process
Architecture
Architecture
Integrate Simulate
Behavioral Circuit Elements
Behavioral Verilog
Topologies
Structural Verilog
Integrate Simulate
Schematic
Schematic
Layout
Layout
Integrate Simulate
Extract
Extract
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Design Process (cont.)

• Both teams worked somewhat independently
• Analog side used behavioral sinc filter
• Digital side used simulated inputs
• When either team takes a major step, make sure
  everything still works
• Compare structural to behavioral, schematic to
  structural, etc
• When possible, put the two halves together

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Major Design Decisions

• Focus on voice specific frequencies 0 10 KHz
• Sets Nyquist clock at 20 KHz
• First order modulator
• Oversampling rate of 256
• Sets oversampled clock at 5.12 MHz
• Second order sinc filter
• Lth order modulator requires L1 order sinc
  filter
• 16 bit resolution
• Mth order sinc filter requires Mlog2(OSR)
  bits
• Designed with NCSU design kit
• Mightve been easier to use GPDK, if used from
  the start

16
Floorplan EvolutionComponent Layout

• Sherif Morcos

17
Floorplan Evolution

• Floorplan changed several times
• Original floorplan
• 18 bit decimator and 2nd order modulator
• Overall chip area 335 µm x 230 µm 77,000 µm²
• Modified floorplan
• 2nd order analog modulator with enormous
  resistors and capacitors (about 150 µm x 50 µm
  7,500 µm² each)
• 3rd order 24-bit digital sinc filter plus PII
  module and clock divider (14,500 transistors)

18
Original Floorplan
19
Floorplan Evolution (contd)

• Final floorplan
• With previous floorplan, might have violated area
  constraint of 300,000 µm²
• Change to analog modulator reduced size of design
• Determined that passive elements could be reduced
  in size considerably
• After modifications, floorplan area was estimated
  at about 400 µm x 340 µm 136,000 µm²
• Final layout grew slightly to 500 µm x 378 µm
  189,000 µm² with slight increase in size of
  passive components

20
Final Floorplan
21
?S Modulator Transistor - Layout
Comparator
D Flip Flop
Differential Op Amp
17 Analog Transistors
22
Decimator Layout
PII Function
256 Clock Divider
Sinc2 Filter
23
Isolation Rings
24
Top Level Layout Digital Verification

• Amar Sharma

25
Final Top Level Layout
26
Final Floorplan
Low Pass Filter
Modulator
Clock Divider
PII
Sinc Filter
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Data Flow Top Level Layout
Low Pass Components
Filtered Signal
Analog Input
Delta Sigma Modulator Components
Wait Period
CLK Divider
Min
Sinc Filter
PII
16-Bits
Out
1-Bit Stream
Max
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Poly Active
Poly density 23.92
Active / Well density 1.01
29
Metal 1
Metal 1 density 25.33
30
Metal 2
Metal 2 density 23.89
31
Metal 3
Metal 3 density 22.53
32
Metal 4
Metal 4 density 0.68
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Digital Verification

• All digital components functionally verified
  previously
• No timing analysis required
• Clocks domains are 5.12 MHz and 20 KHz
• Critical path (two 16 bit adders) are located in
  20 KHz domain
• Optimization - Main focus to ensure signal
  integrity
• Initial layouts had outputs not reaching
  full-rail
• Optimizations widened Vdd and Gnd lines
• Outputs now swing full-rail

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High Output Levels
Before
After
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Sinc Filter extractedRC Output
36
PII extractedRC Output (Max)
37
PII extractedRC Output (Min)
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Analog/Overall Verification Specs Summary

• Huiyi Lim

39
Analog Verification

• Analog half is simulated as ExtractedRC
• Input is a weighted sum of frequencies found in
  the human voice
• Output of analog half is a bitstream
• To make sense of it, behavioral decimator is used
• To get proper results, simulator must be set to
  be as accurate as possible
• Greatly increases running time of simulation

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Analog Verification (cont.)
41
Overall Verification

• Extracted the lowpass filter, modulator, and sinc
  filter together, then simulated
• Used actual outputs from clock divider in
  simulation without including it in simulation
• Input is a simple 2 KHz sine wave

42
Overall Verification (cont.)
43
Chip Specs

• Aspect Ratio 1.3
• Input Bandwidth 0 10 KHz

• Oversampling rate 256
• 16 bit resolution

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Pin Specs

• Inputs
• 2 Analog Inputs
• 12 Wait Period Inputs
• Oversampled Clock Input
• Outputs
• 16bit Output Pins
• 16bit Min Pins
• 16bit Max Pins
• Other
• Vdd Gnd Pins

45
Product Summary

• Achieved first working mixed signal design in
  18-525 history
• Met course objectives
• Low power design (242 µW)
• Small size (500 µm x 370 µm)
• Under 100 pins (55 total pins)
• Developed a practical marketable product