TRD UCrate electronics Status report Power Up Failure Recovery

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TRD U-Crate electronicsStatus reportPower Up /
Failure Recovery

• Wim de Boer, Chan Hoon Chung, Florian Hauler,
  Levin Jungermann, Mike Schmanau, Georg Schwering
• IEKP - Universität Karlsruhe (TH)
• RWTH-Aachen I

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Outline

• QM2 production status of boardsUDR2, UPSFEv2,
  UBPv2, S9011AUv2, S9011B
• Assembled UPD-Box
• Slow Control System Design
• Power-up / Failure Recovery
• Summary

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TRD(U)-Electronics Overviewafter weight reduction
Ucrate TRD electronic crate UBP TRD
backplane UPD TRD power distribution box
V2
V2
UPSFE TRD power supply for front end UDR TRD
data reduction board JINF data concentrator and
link to higher DAQ for TRD UHVG TRD high
voltage generator UFE TRD front end UTE TRD
tube end UHVD TRD high voltage distributor
removed USCM USCM functionality covered partly by
JINFV2
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Full U-crate with QM2 hardware
UHVG
JINF
UDR2
UPSFE
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Status of U-boards

• UDR2 / UPSFEv2 / UBPv2 / S9011AUv2 / S9011B /
  DC-DC converters
• QM2 production and testing at CSIST in Taiwan
  finished.
• December 2004. First slow control tests at
  Prevessin (Andrei, Vladimir, Alexei) using JINFv2
  with full crate at CERN were successful.
• UPD-Box and U-crate currently at Karlsruhe for
  UPD-Box integration and system tests.
• A second set of U-crate boards (later to be used
  for TVT) is ordered from Taiwan for testing and
  development at Prevessin.

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UPD-Box Assembly

• Prototype UPD-Box assembled.
• Electrical tests finished.
• Slow control is working DC/DC converters can be
  switched on or off.
• Complete system test of U-crate and UPD-Box in
  the coming weeks with cosmics test stand.
• Further system test is foreseen in Aachen
  Connection to octagon andoperation with gas
  system. Special attention to noise performance.
• Custom cable tiers used. Do we have to exchange
  them before entering TVT chamber? Which other
  material, Tefzel?
• Before TVT, boards and cabling has to be cleaned.

• ring lug space problems will be solved by
  raising middle bus bars with copper washer.

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Cosmics at Karlsruhe
New cosmics test stand at Karlsruhe for long term
data taking.
Trigger A
PM HV
64 channel strawtube jig
Trigger B
Trigger electronics
Power supply
U-Crate
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U-crate Power Distribution
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S9048/UPSFE connection scheme
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U-crate slow control scheme
x3
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Requirements for JINFv2 Slow Control

• In the current software version During Lecroy
  bus slow control access via JINFv2, event
  processing in DSP is paused. Improved version
  available soon.
• To prevent DAQ performance reduction, a table
  representing slow control registers of S9011AUv2,
  UPSFEv2 and UHVG should be maintained in JINFv2
  memory.
• An access to this table is much faster than a
  Lecroy bus access (64 bit, 500kHz).
• If possible, all registers should be buffered
  UPSFEv2 S9011AUv2 UHVGSpecial care has to be
  taken when buffering trip counters, since they
  are reset after an access.
• HV data should not be older than a defined time.
• JINFv2 slow control processing should be able to
  be started/stopped upon request.
• We are beginning to have experience with the
  system, so requirement list may grow or change

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Dallas Temperature sensors

• 2 Dallas sensors on S9011AUv2 in UPD-Box
• 2 Dallas sensors on each UPSFEv2 in U-crate.3
  UPSFEv2 in U-crate.
• Connected with 2 Dallas buses.
• Topology

UPD-Box
U-crate
somewhere
Bus 1
T
T
T
T
Dallas readout
Bus 2
T
T
T
T
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Power-Up/Failure recovery
Power On (if conditions are safe)
All primary and secondary hardware is on
JMDC (or from ground control) Verify
UPD/U-crate hardware status
OK! Switch off redundant hardware
Not OK! Manual recovery in control center.or
if problem is known and JMDC has explicit
instructions correct problem automatically
Gas ok?
HV ramping
data taking and slow control monitoring (JMDC)
Problem detection
Known problem Automatic treatment in JMDC
Unknown problem Manual failure recovery in
control center
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Summary

• All QM2 boards for TRD are tested and are
  available for space-qualification tests.
• UPD-Box integration completed. Electrical tests
  ok. System tests with U-crate pending.
• Cosmics test stand to verify system performance
  is available.
• First JINFv2 DSP slow control software is
  available (by Andrei). S9011AUv2, UPSFEv2 and
  UHVG can be controlled and monitored.
• OK for flight module production will be given, as
  soon as system tests and space qualification
  tests have been completed. (TVT, vibration, )

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TRD front end simulator (UFS) for TVT at NSPO
During TVT, not enough real front ends will be
available. A device is needed to simulate the
load to the USPFE-boards and to answer the
signals of the UDR2-boards to recognize any
faults.
Load resistors
UPSFE
Heat Interface
Power for front ends
Load resistors
DAC level
DAC
ADC
control signals
UDR2
UFS
Clock ADC
FPGA/DSP
LVDS
digitzed DAC level
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QM2 UPSFE tests Linear regulator test circuit
principle
Personal Computer with Labview Software
I
I/O-Warrior USB Interface Microcontroller
UPSFE linear regulator
DS1803Digital Potentiometer
MOSFET
MAX 890L
RLoad
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Status of U-crate boards

• UDR2 (Data reduction board)
• QM2 production at CSIST in Taiwan completed. 4
  boards delivered to KA.
• UPSFEv2 (Power Supply for Frontends)
• QM2 production at CSIST in Taiwan completed.
• 6 QM2 UPSFEs delivered to KA.
• UBPv2 (backplane)
• QM2 UBPv2 production finished.
• 1 QM2 backplane delivered.
• Slow control functionality tested successfully
  with UPSFEv2, UHVG and JINFv2.

QM2 UDR2
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Status of UPD boards S9011AUv2 and S9011B

• S9011AUv2 for control of DC/DC converters in
  UPD-Box
• S9011AUv2 QM2 production finished at CSIST.All
  boards tested at CSIST.
• S9011B Filter
• S9011B QM2 production finished at CSIST.

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QM2 UPSFE tests Variable load
Max 890L MOSFET
Status LED
Opto-coupler
-2.0V
UPSFEv2
feed back to PC (via MC)
2.0V
DS 1803 Digital Potentiometer
Load resistor
control lines from PC (via MC)
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QM2 UPSFE tests Control software

• Labview Software for UPSFE tests
• automatic testing of 14 UPSFE channels
• ramping load
• reading linear regulator feed back and
  storing switch-off currents.
• monitoring of UPSFE supply currents

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QM2 UPSFE tests Test of slow control
communication
Test of Lecroy communication to S9011AUv2 and
UPSFEv2 using Alexei Lebedevs control
software. (Many thanks to Alexei!!)
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T/U Crates and T/UPD-Boxes produced in Karlsruhe
and ready

• UPD-box mechanics/U-crate mechanics
• QM T/U-crate T/UPD-Box including 22 I-frames for
  DC/DC converters produced in Karlsruhe.
• Surface treatment was done at CSIST!
• Screws procurement was done by MIT.
• Connector procurement ongoing at MIT.

Mechanics are made for old crate/box layout Are
these old (pre-weight-reduction) boxes suitable
for TVTEMI-Tests? New boxes/crates take 4 month
production time at CSIST. Drawings are not yet
delivered.
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TRD(U)-Electronics Overview
Ucrate TRD electronic crate UBP TRD
backplane UPD TRD power distribution
box USCM TRD power controller
UPSFE TRD power supply for front end UDR TRD
data reduction board JINF data concentrator and
link to higher DAQ for TRD UHVG TRD high
voltage generator UFE TRD front end UTE TRD
tube end UHVD TRD high voltage distributor
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QM2 UPSFE testsUPSFE Test-Workbench
geom. address
Monitor lines
status LEDs for UHVG,UDR2 ON/OFF
LeCroy
Dallas Temp. sensor bus
variable load (28x)
UPSFEv2 slot
power connections
USB interface