PowerPC vs. MIPS

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PowerPC vs. MIPS

• By
• Ufuk Kurt
• Xiang Lin

2
Outline

• Introduction
• ISA
• Overall Design
• Pipeline
• PPC Vs. MIPS - Similarities
• PPC Vs. MIPS - Differences
• Summary

3
Introduction

• RISC microprocessor architecture
• Based on POWER architecture
• 1991, Apple-IBM-Motorola (AIM) alliance
• 1994 2006, Apple Macintosh

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ISA
5
Overall Design

• Integer Execution Unit
• Floating Point Unit
• Load/Store Unit (LSU)
• Branch Execution Units
• Memory Management Unit
• Memory Unit
• Cache

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Integer Execution Unit (IU)

• Two single-cycle units (SCIU)
• One multi-cycle unit (MCIU)
• PowerPC 601
• 32 General-purpose register file (GPR)
• Integer exception register (XER)
• Dual-ported
• Feed-forwarding

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Floating Point Unit (FPU)

• 32 64-bit Floating-point register file (FPR) and
• Status and control register (FPSCR)

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Load/Store Unit (LSU)

• Single-cycle, pipelined access to cache
• address calculations
• precision conversion
• sign-extension
• Uses
• a 4-entry load miss buffer
• 6-entry store buffer

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Branch Execution Unit (BPU)

• Link register (LR)
• Count register (CTR)
• Condition register (CR)
• Branch folding
• Uses dynamic branch prediction
• Maintains a 512-entry branch history table with
  two prediction bits
• Keeps a 64-entry branch target address cache

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Memory Management Unit (MMU)

• On-chip tables for address translation
• 4E9 (4 Gigabytes) of physical memory
• 4E15 (4 Petabytes) of virtual memory

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Memory Unit

• 2 entry read
• 3 entry write
• Holds 8 words per entry
• Least recently used (LRU) entry
• Cache to write queue

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Cache

• 32-kByte (write-back) cache
• PowerPC 601
• Unified cache
• Subdivided into 8 pages
• Each page contains 64 cache lines
• Each line subdivided into 2 sectors of 8 32-bits
  words

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Pipeline

• PowerPC 604 processor
• 32 general-purpose registers (GPRs)
• 32 floating-point registers (FPRs)
• Three basic execution units
• Integer
• Floating-point
• Load/store
• A branch processing unit
• A completion unit

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Simplified PowerPC 604
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Pipeline (contd)
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Pipeline (contd)

• Fetch (IF)
• Decode (ID)
• Dispatch (DS)
• Execute (E)
• Complete (C)
• Write back (WB)

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Pipeline (contd)
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PowerPC Vs. MIPS - Similarities

• Pipelined architecture
• Floating point operations
• 32-bits registers
• Branch prediction unit

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PowerPC Vs. MIPS - Differences

• Instruction sets
• Pipeline
• Floating point operation
• Handling hazards
• Efficiency
• Jump instructions
• 64-bit registers

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Summary

• Overall PowerPC is better architecture

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Will PowerPC Die?
22
Intel Pentium Vs. PowerPC
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Intel Core Duo Vs. PowerPC
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Intel Core 2 Vs. PowerPC
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Future of PowerPC

• Will PowerPC die?
• Apple Macs
• Xbox 360 Elite PPC 3 cores 3.2 GHz
• Wii - 729MHz Broadway
• Game Cube - 485MHZ Gekko