Missing figures from last class

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Missing figures from last class

• Decoder
• Mux
• ½ Adder
• Full Adder
• 1-bit ALU
• 4-bit ALU

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Muxes can be combined.
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1-Bit ALU
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4 Bit ALU
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Sequential Circuits
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• Combinational circuits lack the abiltity to store
  and remember particular bit patterns. They have
  no memory (except ROMs) and cannot keep track of
  system state.
• Current state of a Sequential circuit depends not
  only on current input but on all previous input

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Flip-Flops

• S-R Latch
• 2 Inputs S and R for set and reset
• 2 outputs Q and Q with Q always equal to the
  complement of Q
• Bistable Q is always equal to 0 or 1 and Q is
  always its complement.

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S-R Latch

• The set-reset latch
• output depends on present inputs and also on past
  inputs

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Latches and Flip-flops

• Output is equal to the stored value inside the
  element (don't need to ask for permission to
  look at the value)
• Change of state (value) is based on the clock
• Latches whenever the inputs change, and the
  clock is asserted
• Flip-flop state changes only on a clock
  edge (edge-triggered methodology)

"logically true", could mean electrically low
A clocking methodology defines when signals can
be read and written wouldn't want to read a
signal at the same time it was being written
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• Problem with SR Latch. When both S and R are 1
  for a moment and then switched to 0, the output
  is unstable and unpredictable. A race condition
  develops where Q and Q switch values repeatedly
  until (due to real-world imperfections) one state
  becomes stable.

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Other Flip-Flops

• DDerived from S-R flip-flop by using an inverter
  to assure R is always S
• J-K Flip-Flop designed to allow 1 1 as possible
  input. Version in book requires an instantaneous
  clock to prevent instability. Usually its seen
  in the Master-Slave format where the first stage
  is active while Clock is high and the second
  stage only while clock is low and first stage is
  latched.

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D-latch

• Two inputs
• the data value to be stored (D)
• the clock signal (C) indicating when to read
  store D
• Two outputs
• the value of the internal state (Q) and it's
  complement

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D flip-flop

• Output changes only on the clock edge

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Registers

• An essential element of the computer is the
  Register. We can now construct a register as a
  circuit consisting of one or more Flip-Flops
  sharing a common clock.
• Master-Slave flip-flops may be need to be used to
  prevent feedback, but well just draw them simply
  using SR Flip Flops

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Simple Parallel Register

• Picture to come

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Shift Register

• Can accept and/or transfer data serially
• A simple serial buffer is shown, but this diagram
  could be combined with the Parallel register to
  provide several needed functions.

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Shift Register

• Picture to come

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Ripple Counter

• Obtained by wiring a set of JK flip-flops in
  sequence using the fact that a 11 input toggles
  the value of Q on the falling edge of the clock.
  Note that the low bit is pictured first.

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Ripple Counter
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Clocks

• Basic pulse may be generated by a clock device,
  quartz crystal perhaps, that determines the
  overall speed of the transitions.
• Clock to any device will in general be derived
  from this together with control signals. For
  example, the clock may be the AND of a control
  bit and the system clock.

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Clocks continued

• Events in the computer happen at various times
  related to the clock.
• Falling edge
• Rising edge (invert the clock signal)
• While clock 0 or clock 1
• Derived clock. Note the effect of ORing the clock
  signal with the Q0 output in the ripple counter
  to produce an asymmetric clock pulse.

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State Elements

• Unclocked vs. Clocked
• Clocks used in synchronous logic
• when should an element that contains state be
  updated?

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Register File

• Built using D flip-flops