EnergyEfficient Transistors Alan Seabaugh www.nd.edunano

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Energy-EfficientTransistorsAlan
Seabaughwww.nd.edu/nano
Institut Joef Stefan, Ljubljana, Slovenia, 24
Oct. 2007
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University of Notre Dame Notre Dame, Indiana
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University of Notre Dame
Edward Sorin, founder, 1842
Notre Dame circa 1866
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University of Notre Dame Electronic Materials,
Devices, and Circuits (EMD)
Founded 1842, Engineering College 1873 First
wireless transmission in North America
1899 Undergraduates 8275, Graduate students 3142
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Notre Dame Nanofabrication Facility
5000 sq. ft. CMOS III-V magnetics
molecular processes
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Site of Nanofabrication Facility - Opens 2010
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Site of Nanofabrication Facility - Opens 2010
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Doug Hall
Debdeep Jena
Tom Kosel
Patrick Fay
Gary Bernstein
Jim Merz
Alexander Mintairov
Alexei Orlov
Wolfgang Porod
Grace Xing
Craig Lent
Alan Seabaugh
Greg Snider
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Notre Dame Research 2007
High Performance Transistors III-V MOSFETs
(PF-DH-AS-TK) Single electron transistors
(AO-GS-PF) X-W-band InP and GaAs LNA, PAs
(PF) Nitride-Based Electronics GaN/InGaN MBE
Growth (DJ) Transport theory (DJ) HEMTs and HBTs
(DJ-GX) GaN sensors (GX-DJ) GaN/Ge junctions
(AS-DJ-GX) Tunneling Devices and
Circuits Low-subthreshold-swing transistors
(AS-TK) Ge and III-V detectors (AS-PF) III-V SRAM
(AS) MIM IR detectors (PF-GB-WP) Energy
scavenging (AS) Carbon-Based Electronics Graphene
(DJ-GX-GS) Carbon nanotube FETs (GS) Materials
Characterization and Nanofabrication Transmission
electron microscopy (TK) III-V oxidation (DH)
Quantum-Dot Cellular Automata Molecular-based
(CL), Magnetics (GB-WP-AO) Silicon-based
(GS-AO) Cellular Neural Networks
(WP-GB-PF) Nanowires, Networks, and
Transport CdS, CdSe, CdTe, PbSe
(TK-DJ) Nitride-based (DJ), MoS2 and W5O14
(AS) Dielectrophoretic assembly (GX) Fundamental
Limits of Computation (CL) Quilt Packaging
(GB-PF-GS) Photonic Devices Quantum dot
spectroscopy (AM-JM) InP-based 40 GHz
photodetectors (PF) Photovoltaics/thermophotovolta
ics (PF) Diode lasers (DH) High-index waveguides
(DH) Bioelectronics Sensors and interfaces
(WP-GX) Quantum dot sensors (CL-GS-AO) Inductively
-coupled implants (GB) Microfluidic needles
(GB-WP)
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Energy-Efficient TransistorsOutline

• Introduction
• Field-effect transistors
• ENERGY LOSS, POWER DISSIPATION
• SUBTHRESHOLD SWING
• Field-effect interband tunnel transistors
• INTERBAND TUNNELING
• LOW SUBTHRESHOLD SWING TUNNEL TRANSISTORS
• RAPID MELT GROWTH GE JUNCTIONS
• Summary

SOI silicon-on-insulator
MOSFET metal oxide semiconductor field effect
transistor
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Natural selection for electron devices- survival
of the smaller, more energy-efficient technology
CMOS Wanlass, 1963
MOSFET Kahng, 1961
Bipolar transistor Shockley, 1947
vacuum tube Fleming 1904
MOSFET metal oxide semiconductor field effect
transistor CMOS complementary MOS low power
circuit
S. Thompson et al. A 90 nm logic technology
featuring strained-silicon, IEEE Trans. Electron
Dev. 51, 1790-1797 (2004).
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Power Density Doubling Every Four Years
New Microarchitecture Challenges in the Coming
Generations of CMOS Process Technologies Fred
Pollack, Intel Corp. Micro32 conference key note
- 1999. Courtesy Avi Mendelson, Intel.
1000
100
Pentium 4
03
99
Pentium III
95
Pentium II
10
91
Pentium Pro
PVI 75 W _at_ 1.5 V 50 A!
87
Pentium
i386
i486
83
1
1.5m
1m
0.7m
0.5m
0.35m
0.25m
0.18m
0.13m
0.1m
0.07m
www.unix-ecs.umass.edu/mheath/teaching/power_lect
...
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Natural selection for electron devices- survival
of the most energy-efficient
Tunnel Transistors
CMOS Wanlass, 1963
Quantum-dot cellular automata
CMOS 9 nm node 2016
MOSFET Kahng, 1961
CMOS 18 nm node 2010
Bipolar transistor Shockley, 1947
Spin transistors Nanomechanical transistors
CMOS 25 nm node 2007
vacuum tube Fleming 1904
MOSFET metal oxide semiconductor field effect
transistor CMOS complementary MOS low power
circuit
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Metal oxide semiconductor field-effect transistor
(MOSFET)
equilibrium
oxide/nitride spacer
EF
CB
ppolySi gate
1.2 nm gate oxide
VB
off
CB
EF
source
drain
VB
nSi
nSi
on
CB
EF
p-Si
VB
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Metal oxide semiconductor field-effect transistor
(MOSFET)
oxide/nitride spacer
ppolySi gate
1.2 nm gate oxide
source
drain
nSi
nSi
p-Si
45 nm gate n-MOSFET (TEM)
S. Thompson et al. A 90 nm logic technology
featuring strained-silicon, IEEE Trans. Electron
Dev. 51, 1790-1797 (2004).
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Au-WS2 nanotube
25 nm
p-MOSFET90 nm node
gate
Remskar et al. Adv. Mat. 12, 814 (2000)
source
drain
S. Thompson et al. A 90 nm logic technology
featuring strained-silicon, IEEE Trans. Electron
Dev. 51, 1790-1797 (2004).
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WS2 tubes nanobuds, Remskar, Virsek, Jesih,
Nanolett. submitted 2007
Thompson et al. p-MOSFET
S. Thompson et al. A 90 nm logic technology
featuring strained-silicon, IEEE Trans. Electron
Dev. 51, 1790-1797 (2004).
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Size Comparison Si MOSFET vs. MoS2 nanotube
MoS2 nanotube Remskar 2006
R. Chau et al., Benchmarking nanotechnology for
high-performance and low-power logic transistor
applications IEEE Trans. Nanotechnol. 4, 153-158
(2005).
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65 nm Node 0.494 mm2 6-transistor-SRAM Cellsize
comparison with WS2 fullerine
Remskar 2006
500 nm
nm 56 120 120 80
LG WAC WDR WLD
988 nm
S. Ohbayashi, et al. 2006 Symp. VLSI Circ. Dig.
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Die micrograph (5.7 x 6.6 mm2)Intel 44 Mbit
ultra-low-power SRAM
65 nm node cell size 0.667 mm2 VDD 1.2 to 0.5
V
Y. Wang et al. A 1.1GHz 12 µA/Mb-leakage SRAM
design in 65 nm Ultra-Low-Power CMOS with
Integrated Leakage Reduction for Mobile
Applications ISSCC 2007 324-326.
.
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Dynamic Power Dissipation
R
Energy to charge a capacitor
V
VDD
C
Energy stored in a capacitor
Energy (power) dissipated in charging a capacitor
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Complimentary MOS (CMOS) Power Dissipation
RON
V
VDD
C
VDD
VIN
VOUT
GND
Lower VDD challenge is to do this without
sacrificing current drive or increasing gate
leakage
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Subthreshold swing sets the minimum active power
dissipation in MOSFETs
n-MOS
LG 45 nm
100
100 mV/dec
10-1
mV decade
10-2
ID (mA/mm)
0.8 V for Ion/Ioff 103
10-3
MOSFET limit S ln10(kT/q) 60 mV/decade, but
increases with scaling
10-4
10-5
0 0.5 1.0
VGS (V)
Intel 90 nm MOSFET technology Ghani et al. IEDM
2003.
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Energy-Efficient TransistorsOutline

• Introduction
• Field-effect transistors
• ENERGY LOSS, POWER DISSIPATION
• SUBTHRESHOLD SWING
• Field-effect interband tunnel transistors
• INTERBAND TUNNELING
• LOW SUBTHRESHOLD SWING TUNNEL TRANSISTORS
• RAPID MELT GROWTH GE JUNCTIONS
• Summary

SOI silicon-on-insulator
MOSFET metal oxide semiconductor field effect
transistor
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Interband Tunnel Junction
depletion region
p
n
EC
EV
EF
(e)
(c)
(d)
(b)
(a)
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Field-effect Zener tunnel transistor
source
drain
oxide
n
p
unbiased tunnel tunction
gate fully depletes channel to create
normally-off device
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Low-Subthreshold-Swing Tunnel Transistor
TechnologyApproach

• Complementary n and p channel
• Equal currents at equal gate lengths

OFF VGS VDS 0 fully depleted channel
ON VGS VDS 0.2 V Zener tunneling turn-on
Simulation Al2O3 gate oxide, pFET gate Al, nFET
Au
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Tunneling Current in Si pn Junctions
Taur et al. IEDM 1998
junction electric field
reverse bias
EC
qVeff
EV
EFP
EFN
Reverse junction bias of 1 V
Esaki tunnel junction
Agreement spans 8 orders of magnitude
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Engineering Subthreshold Swing


EC
qVeff
qVeff
qVeff
EV
EFP
EFN
EFN
(1)
(2)
x
Two way to reduce S not limited by kT
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Maximizing tunnel current
High performance relative to Si MOSFET possible
using Ge and III-V on insulator channels
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Tunnel Transistors vs. Scaled CMOS
Enables 10x power reduction, with 4x speed hit
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Rapid Melt Growth of Ge Tunnel Junctions
Schematic device cross section of the rapid melt
growth process drawn to scale in the vertical
direction. (a) Ge is doped n by rapid thermal
diffusion of P followed by Al deposition,
patterning, and etching. (b) A plasma nitride cap
is applied. (c) At the peak anneal temperature
(600 ºC in this example) with 100 nm Al cap, 110
nm of Ge is consumed. (d) On cooling, a
heavily-doped pGe layer is grown for this
example, from 600 ºC, a 60 nm layer is grown.
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1000
938 C
L
800
Liquidus line
660 C
TP
LGe
600
Temperature C
pGe
TE 420 C
400
5
51.6
99.6
Ramp down p Ge growth
Ramp up melt forms
200
95
20
40
60
80
90
100
0
Ge
Weight Percent Germanium
Al
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Ge tunnel diode current-voltage characteristics
vs. rapid-melt-growth anneal
without silicon nitride cap
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Ge tunnel diode peak current densities vs.
annealing temperatures with a 50 nm Si3N4 cap.
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Optical micrographs showing the dependence of
surface morphology on the presence or absence of
a cap during rapid melt growth of pGe.
50 nm Si3N4 cap
no cap
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Transmission electron microscopy of large area
AlGe-pn tunnel junction after RTA
100 nm Al on Ge 600 C RTA
Lattice image shows clean doping interface
without defects
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Ge TD electron beam pattern 2007
300 nm
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First sub-60 mV/dec tunnel transistor
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Energy-Efficient Transistors (summary)1.
Technology selection is driven by energy
efficiency2. Beyond CMOS, devices must become
more efficient3. Concepts for low subthreshold
swing tunnel transistors4. Rapid Ge melt-growth
process shows high current density 5. First
less-than-60-mV/decade Si tunnel transistor
demonstrated in August - Berkeley6. Race is on
for tunnel junctions with high current density
and high performance relative to CMOS
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Acknowledgements SRC/NIST, AmberWave, Intel,
ONR, DARPA